USB-PD EPR and PMBus regulator assumptions in Jetson Thor reference design

I am designing a custom carrier board for Jetson Thor as part of my master’s thesis. The main focus of the work is the power delivery architecture including USB-PD and high-power input handling.

I am currently working on the USB-PD power path and am following NVIDIA’s reference schematics. In the reference design the USB-PD controller interfaces via PMBus to an external buck regulator which is the MP8856. This device is still pre-release and not available for purchase. In addition my design target is up to 60 V input voltage which also excludes the MP8856.

Because of this I am evaluating alternative PMBus-capable buck regulators such as the MP8880A, LTC3889 or other vendor devices. The USB-PD controller I plan to use is the same as in the reference design.

My design goal is to support USB-PD EPR. At a minimum I want EPR to work as a sink and support standard voltage range operation as a source. I am aware that NVIDIA only enables 5 V source operation in the reference design which would also be a valid fallback option.

Since this is my first USB-PD design I am trying to understand how tightly coupled the firmware and PMBus interaction is to the specific regulator used in the reference design.

My main questions are

  • Does the USB-PD controller firmware used in the Jetson Thor reference design rely on MP8856-specific PMBus registers or command behavior

  • Is it possible to replace the MP8856 with another PMBus-compatible buck regulator and only adapt configuration parameters without modifying firmware

  • Which PMBus command subset is assumed by the reference design

I am also trying to understand how voltage negotiation is expected to behave if the negotiated USB-PD voltage cannot actually be generated by the power stage. For example if USB-PD negotiates 20 V but the buck regulator input or configuration cannot reach that voltage.

  • Is the expected approach to only advertise PDOs that are guaranteed to be achievable

  • Is there any feedback path via PMBus that the USB-PD controller uses to detect such conditions

In short I am trying to determine whether the PMBus-controlled buck in the Jetson Thor USB-PD design is meant to be largely interchangeable or whether the reference design implicitly assumes the MP8856 in ways that affect firmware behavior especially when targeting USB-PD EPR.

Any clarification from NVIDIA or from others who have worked with Jetson Thor USB-PD designs would be very helpful. Thanks!

Thank you for the post and welcome back to the forum.

I understand your questions and don’t need any clarifications right now but will need to check with my team. I should have some answers soon.

Looking at the documentation for the CYPD8225-97BZXI, it mentions contacting Infineon’s local support team for application diagrams for EPR >=28V. Regardless, Infineon’s support team will be better suited to answering your main questions regarding the firmware, external buck regulator, and their interaction for your specific usecase.

In general, only supported PDOs should be advertised by the source/requested by the sink.

PMBus is implementation-specific so there is no straightforward answer. Infineon may be able to support once specific components/ICs are selected.

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