Using simple sometimes doesn't work

My platform is orin, we use external PWM trigger to synchronize between multiple lenses, the lens is controlled by the pulse width to control the exposure. The commands to control exposure are as follows:

echo 99800000 > /sys/class/pwm/pwmchip2/pwm0/duty_cycle

The code for simple is as follows:

import RPi.GPIO as GPIO
import time

output_pins = {
    'JETSON_XAVIER': 18,
    'JETSON_NANO': 33,
    'JETSON_NX': 33,
    'JETSON_TX2_NX': 32,
    'JETSON_ORIN': 18,
    'JETSON_ORIN_NX': 33,
output_pin = output_pins.get(GPIO.model, None)
if output_pin is None:
    raise Exception('PWM not supported on this board')

def main():
    # Pin Setup:
    # Board pin-numbering scheme
    # set pin as an output pin with optional initial state of HIGH
    GPIO.setup(output_pin, GPIO.OUT, initial=GPIO.HIGH)
    p = GPIO.PWM(output_pin, 10)
    val = 100
    incr = 5

    print("PWM running. Press CTRL+C to exit.")
        while True:
            #if val >= 100:
             #   incr = -incr
            #if val <= 0:
            #    incr = -incr
            #val += incr

if __name__ == '__main__':

We will start the simple script first, and then use the command to control the exposure. But I ran into a problem when I set the value above 99800000 and there was no trigger signal. May I ask why?

Hi 1508723374,

Are you using the devkit or custom board for AGX Orin?
What’s your Jetpack version in use?

What’s the current period for PWM

$ cat /sys/class/pwm/pwmchip2/pwm0/period

Does the PWM work as expected if you set the value equal to 99800000 or less than it?

Yes, I used a custom adapter to connect four camera.

xxx@xxx-desktop:~$ cat /etc/nv_tegra_release
# R35 (release), REVISION: 3.1, GCID: 32827747, BOARD: t186ref, EABI: aarch64, DATE: Sun Mar 19 15:19:21 UTC 2023
xxx@xxx-desktop:~$ cat /sys/class/pwm/pwmchip2/pwm0/period

It works when I set it 200000~99800000.

99800000 seems resulting 99.8% duty cycle. What the range of the duty cycle would you need for your use case?

I need it to be about 10000~99990000

Could you share the result of the following command? (if you are using pwm5 from 40-header pins)

$ cat /sys/kernel/debug/bpmp/debug/clk/pwm5/parent

99800000 can work normally, 998100000 can not work, there is no difference between the two.

xxx@xxx-desktop:~$ echo 99800000 > /sys/class/pwm/pwmchip2/pwm0/duty_cycle
xxx@xxx-desktop:~$ sudo cat /sys/kernel/debug/bpmp/debug/clk/pwm5/parent  
xxx@xxx-desktop:~$ echo 99810000 > /sys/class/pwm/pwmchip2/pwm0/duty_cycle 
xxx@xxx-desktop:~$ sudo cat /sys/kernel/debug/bpmp/debug/clk/pwm5/parent  



xxx@xxx-desktop:~$ sudo cat /sys/kernel/debug/pwm
[sudo] password for xxx: 
platform/39c0000.tachometer, 1 PWM device
 pwm-0   ((null)              ): period: 0 ns duty: 0 ns polarity: normal

platform/32f0000.pwm, 1 PWM device
 pwm-0   ((null)              ): period: 0 ns duty: 0 ns polarity: normal

platform/32c0000.pwm, 1 PWM device
 pwm-0   (sysfs               ): requested enabled period: 100000000 ns duty: 99810000 ns polarity: normal

platform/32a0000.pwm, 1 PWM device
 pwm-0   (pwm-fan             ): requested enabled period: 45334 ns duty: 11200 ns polarity: normal

platform/3280000.pwm, 1 PWM device
 pwm-0   ((null)              ): period: 0 ns duty: 0 ns polarity: normal

I’ve checked with internal.
The clock rate of parent clock (pllp_out0) for pwm5 is 408M, which results in max rate at 1.5M (clk_rate / (256 * 1))
You could find more details in TRM document (PWM->Programming Guidelines).

Please configure pwm period to 1.5M and try different value for duty cycle.

According to the formula, it is not clear why there is a limit of 200000~99800000. Because the project requires that the hardware trigger needs to be triggered ten times per second, so the period here can only be set to 100000000, and I hope that the duty cycle can be set to 99.99% on this basis. There is also how I can determine the current PWM5 clock size.

Do you mean 10Hz? Why you need to configure the period to 100M?

It is relating to the clock accuracy.
Please just configure the /sys/class/pwm/pwmchip2/pwm0/period to 1000000 and try with different duty cycle (0%-100%)

The current clock input is 408MHz.

Thank you very much for your patient reply. I have tried the method you mentioned, and his working range is between 2000 and 998000, which is a hundred times smaller than the previous phenomenon.

I think of it this way, 100m =100ms, 1S/100ms =10 times. It’s the only way to actually trigger ten times.

hello, KevinFFFModerator

Sorry that I’m not clear about these relationship.
Could you help to clarify and explain more details? Why 10Hz (10 times/second) results period to be 100M?

Okay, you’re not quite understanding what I’m saying, so let’s ignore the frequency. This period is measured in nanoseconds, and if I set the period to 100000000 ns, that means I have 10 cycles per second. The number of cycles is the trigger frequency I need.

Hello KevinFFF, is there any other way I can set it to 99990000?

Could you try using clk_32k as parent clock and configure 256 as rate?

# cd /sys/kernel/debug/bpmp/debug/clk/pwm5
# echo clk_32k > parent
# echo 256 > rate
# cat rate

Setting the parent clock according to your method still does not work, setting 99990000 is still a problem.

Hi @1508723374,

What do you mean about “not work”?
Could you configure this value w/o modifying the parent clock for pwm0?
Or there’s no waveform output when you configure this value.

# echo 10000 > period