I transported driver of nvp6324 to tegracam framework, but got errors when capturing frames:
misc tegra_camera_ctrl: tegra_camera_update_isobw: Warning, Requested ISO BW 1476562 has been capped to VI’s max BW 1000000
[ 213.877749] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[ 214.089721] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65517, flags: 0, err_data 512
[ 214.114091] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 214.175388] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 112, err_data 10486370
[ 214.189587] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65326, flags: 0, err_data 512
[ 214.189817] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65456, flags: 0, err_data 512
[ 214.342068] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 112, err_data 10486370
[ 214.380806] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 214.389569] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65429, flags: 0, err_data 512
[ 214.389777] tegra194-vi5 15c10000.vi: corr_err: discarding frame 57270, flags: 0, err_data 512
[ 214.441917] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 112, err_data 10486370
[ 214.513957] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 214.522937] tegra194-vi5 15c10000.vi: corr_err: discarding frame 57273, flags: 0, err_data 512
[ 214.523148] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65434, flags: 0, err_data 512
[ 214.575257] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 112, err_data 10486370
[ 214.680464] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 214.689778] tegra194-vi5 15c10000.vi: corr_err: discarding frame 180, flags: 0, err_data 512
[ 214.689985] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65471, flags: 0, err_data 512
[ 214.741897] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 112, err_data 10486370
[ 214.780521] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 214.789758] tegra194-vi5 15c10000.vi: corr_err: discarding frame 57281, flags: 0, err_data 512
[ 214.789935] tegra194-vi5 15c10000.vi: corr_err: discarding frame 65506, flags: 0, err_data 512
[ 214.838117] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 214.842009] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 546
[ 214.842237] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 131072
[ 214.980719] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 215.104683] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 215.142007] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 215.180412] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 215.241886] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 215.408582] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 546
[ 215.447404] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 215.508580] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 215.580467] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 215.641857] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 215.841232] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 215.841896] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 546
[ 215.875176] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 215.878608] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 215.941901] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 215.980512] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.080416] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.113799] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.175193] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 216.207838] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.213778] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 32, err_data 162
[ 216.241878] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.275226] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 216.347165] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.380622] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.441866] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 216.580344] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 216.641854] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 240, err_data 10486370
[ 216.780614] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 160, err_data 162
[ 219.373730] tegra194-vi5 15c10000.vi: no reply from camera processor
[ 219.373907] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[ 219.374048] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[ 219.377436] tegra194-vi5 15c10000.vi: unexpected response from camera processor
[ 219.377619] tegra194-vi5 15c10000.vi: vi capture setup failed
[ 219.377815] tegra194-vi5 15c10000.vi: fatal: error recovery failed
Here is my dtsi:
/ {
host1x {
vi@15c10000 {
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
nvp6324_vi_in0: endpoint {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&nvp6324_csi_out0>;
};
};
};
};
nvcsi@15a00000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
nvp6324_csi_in0: endpoint@0 {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&linvp6324_nvp6324_out0>;
};
};
port@1 {
reg = <1>;
nvp6324_csi_out0: endpoint@1 {
remote-endpoint = <&nvp6324_vi_in0>;
};
};
};
};
};
};
i2c@3180000 {
ov5693_c@31 {
compatible = "nextchip,nvp6324_mipi";
/* I2C device address */
reg = <0x31>;
/* V4L2 device node location */
devnode = "video0";
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&bpmp_clks TEGRA194_CLK_EXTPERIPH1>,
<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
clock-frequency = <27000000>;
//reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
//pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
//vana-supply = <&p2822_avdd_cam_2v8>;
//vif-supply = <&p2822_vdd_1v8_cvb>;
/* Sensor output flip settings */
//vertical-flip = "true";
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
* Incase of virtual HW devices, use virtual
* For SW emulated devices, use host
*
* phy_mode = "";
* PHY mode used by the MIPI lanes for this device
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* == Source Control Settings ==
*
* Gain factor used to convert fixed point integer to float
* Gain range [min_gain/gain_factor, max_gain/gain_factor]
* Gain step [step_gain/gain_factor is the smallest step that can be configured]
* Default gain [Default gain to be initialized for the control.
* use min_gain_val as default for optimal results]
* Framerate factor used to convert fixed point integer to float
* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
* Default Framerate [Default framerate to be initialized for the control.
* use max_framerate to get required performance]
* Exposure factor used to convert fixed point integer to float
* For convenience use 1 sec = 1000000us as conversion factor
* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
* Default Exposure Time [Default exposure to be initialized for the control.
* Set default exposure based on the default_framerate for optimal exposure settings]
*
* gain_factor = ""; (integer factor used for floating to fixed point conversion)
* min_gain_val = ""; (ceil to integer)
* max_gain_val = ""; (ceil to integer)
* step_gain_val = ""; (ceil to integer)
* default_gain = ""; (ceil to integer)
* Gain limits for mode
*
* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* step_exp_time = ""; (ceil to integer)
* default_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
* min_framerate = "";
* max_framerate = "";
* step_framerate = ""; (ceil to integer)
* default_framerate = ""; (ceil to integer)
* Framerate limits for mode (fps)
*/
mode0 { // nvp6324_MODE_1280*720
mclk_khz = "27000";
num_lanes = "2";
tegra_sinterface = "serial_c";
phy_mode = "DPHY";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
mode_type = "yuv";
pixel_phase = "uyvy";
csi_pixel_bit_depth = "16";
readout_orientation = "0";
line_length = "1800";
inherent_gain = "1";
mclk_multiplier = "28";
pix_clk_hz = "756000000";
gain_factor = "10";
min_gain_val = "10";/* 1DB*/
max_gain_val = "160";/* 16DB*/
step_gain_val = "1";
default_gain = "10";
min_hdr_ratio = "1";
max_hdr_ratio = "1";
framerate_factor = "1000000";
min_framerate = "1816577";/*1.816577 */
max_framerate = "30000000";/*30*/
step_framerate = "1";
default_framerate = "30000000";
exposure_factor = "1000000";
min_exp_time = "34";/* us */
max_exp_time = "550385";/* us */
step_exp_time = "1";
default_exp_time = "33334";/* us */
embedded_metadata_height = "0";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
linvp6324_nvp6324_out0: endpoint {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&nvp6324_csi_in0>;
};
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <2>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <8>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. 鈥渞ear鈥?or 鈥渇ront鈥?
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "nvp6324_bottom_mipi31";
position = "front";
orientation = "0";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "nvp6324_v1 2-0031";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/nvp6324@31";
};
};
};
};
};
after I did these below:
To enable logs from user-space for more details
sudo su
kill the process of argus_daemon/nvargus-daemon or nvcamera-daemon
export enableCamPclLogs=5
export enableCamScfLogs=5
/usr/sbin/argus_daemon(nvargus-daemon) option for argus
/usr/sbin/nvcamera-daemon option for gst-launch
launch camera from another console
To enable trace for more information
echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 2 > /sys/kernel/debug/camrtc/log-level
echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
echo > /sys/kernel/debug/tracing/trace
cat /sys/kernel/debug/tracing/trace
I got：
root@nvidia-xavier:/home/hitron/hitron/firmware# cat /sys/kernel/debug/tracing/trace
tracer: nop
entries-in-buffer/entries-written: 35/35 #P:8
_-----=> irqs-off
/ _----=> need-resched
| / _—=> hardirq/softirq
|| / _–=> preempt-depth
||| / delay
TASK-PID CPU# |||| TIMESTAMP FUNCTION
| | | |||| | |
kworker/0:2-1296 [000] .... 259.974862: rtos_queue_peek_from_isr_failed: tstamp:8322429346 queue:0x0bcbcf78
kworker/0:2-1296 [000] .... 260.142869: rtos_queue_peek_from_isr_failed: tstamp:8327429353 queue:0x0bcbcf78
kworker/0:2-1296 [000] .... 260.310838: rtos_queue_peek_from_isr_failed: tstamp:8332429344 queue:0x0bcbcf78
kworker/0:2-1296 [000] .... 260.422925: rtos_queue_peek_from_isr_failed: tstamp:8337429344 queue:0x0bcbcf78
kworker/0:2-1296 [000] .... 260.590895: rtos_queue_peek_from_isr_failed: tstamp:8342429342 queue:0x0bcbcf78
kworker/0:2-1296 [000] .... 260.758834: rtos_queue_peek_from_isr_failed: tstamp:8347429342 queue:0x0bcbcf78
[b]then v4l2-ctl --set-fmt-video=width=1280,height=720,pixelformat=UYVY --stream-mmap --stream-count=100 -d /dev/video0
the error log：[/b]
[ 343.898810] misc tegra_camera_ctrl: tegra_camera_update_isobw: Warning, Requested ISO BW 1476562 has been capped to VI’s max BW 1000000
[ 343.977610] [RCE] Configuring VI GoS.
[ 343.977944] [RCE] VM GOS[#0] addr=0xe4900000
[ 343.978473] [RCE] VM GOS[#1] addr=0xe4901000
[ 343.978484] [RCE] VM GOS[#2] addr=0xe4902000
[ 343.978494] [RCE] VM GOS[#3] addr=0xe4903000
[ 343.978503] [RCE] VM GOS[#4] addr=0xe4904000
[ 343.978513] [RCE] VM GOS[#5] addr=0xe4905000
[ 344.091916] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[ 344.148467] [RCE] VI GOS[#0] set to VM GOS[4] base 0xe4904000
[ 344.428930] [RCE] ERROR: heartbeat-task.c:97 [heartbeat_wdt_fiq_callback] “WDT irq died. RCE in bad state.”
[ 344.580151] tegra186-cam-rtcpu bc00000.rtcpu: Alert: Camera RTCPU gone bad! restoring it immediately!!
[ 346.651741] tegra194-vi5 15c10000.vi: no reply from camera processor
[ 346.651943] tegra194-vi5 15c10000.vi: uncorr_err: request timed out after 2500 ms
[ 346.652120] tegra194-vi5 15c10000.vi: err_rec: attempting to reset the capture channel
[ 346.652404] tegra194-vi5 15c10000.vi: vi_capture_release: control failed, errno 1
[ 346.654113] tegra194-vi5 15c10000.vi: unexpected response from camera processor
[ 346.654297] tegra194-vi5 15c10000.vi: vi capture setup failed
[ 346.654440] tegra194-vi5 15c10000.vi: fatal: error recovery failed
[ 346.667657] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
The trace tell didn’t receive any validate data from the MIPI bus. You may need to probe to make sure of it.
after I start to capture video，
I got this：
kworker/0:4-2262 [000] … 119.278722: rtcpu_nvcsi_intr: tstamp:3925845007 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:8 status:0x0000000a
kworker/0:4-2262 [000] … 119.278722: rtcpu_nvcsi_intr: tstamp:3925845007 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:15 status:0x0000000a
kworker/0:4-2262 [000] … 119.278722: rtcpu_nvcsi_intr: tstamp:3925846232 class:GLOBAL type:STREAM_NOVC phy:0 cil:0 st:2 vc:0 status:0x00000001
kworker/0:4-2262 [000] … 119.278723: rtcpu_nvcsi_intr: tstamp:3925846232 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:1 status:0x0000000a
kworker/0:4-2262 [000] … 119.278723: rtcpu_nvcsi_intr: tstamp:3925846232 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:8 status:0x0000000a
kworker/0:4-2262 [000] … 119.278724: rtcpu_nvcsi_intr: tstamp:3925846232 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:15 status:0x0000000a
kworker/0:4-2262 [000] … 119.278725: rtcpu_nvcsi_intr: tstamp:3925846232 class:CORRECTABLE_ERR type:STREAM_NOVC phy:0 cil:0 st:2 vc:0 status:0x00000001
kworker/0:4-2262 [000] … 119.278725: rtcpu_nvcsi_intr: tstamp:3925846232 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:1 status:0x0000000a
kworker/0:4-2262 [000] … 119.278726: rtcpu_nvcsi_intr: tstamp:3925846232 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:8 status:0x0000000a
kworker/0:4-2262 [000] … 119.278726: rtcpu_nvcsi_intr: tstamp:3925846232 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:2 vc:15 status:0x0000000a
kworker/0:4-2262 [000] … 119.278726: rtcpu_nvcsi_intr: tstamp:3925847774 class:GLOBAL type:STREAM_NOVC phy:0 cil:0 st:2 vc:0 status:0x00000001
kworker/0:4-2262 [000] … 119.278727: rtcpu_nvcsi_intr: tstamp:3925847774 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:1 status:0x0000000a
kworker/0:4-2262 [000] … 119.278727: rtcpu_nvcsi_intr: tstamp:3925847774 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:8 status:0x0000000a
kworker/0:4-2262 [000] … 119.278727: rtcpu_nvcsi_intr: tstamp:3925847774 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:2 vc:15 status:0x0000000a
kworker/0:4-2262 [000] … 119.278728: rtcpu_nvcsi_intr: tstamp:3925847774 class:CORRECTABLE_ERR type:STREAM_NOVC phy:0 cil:0 st:2 vc:0 status:0x00000001
The REG NVCSI_STREAM_0_CORRECTABLE_ERR_INTR_STATUS_NOVC_0 tell err_intr_stat_ph_ecc_multi_bit_err: packet header multi-bit ECC error.
kworker/0:4-2262 [000] … 119.278726: rtcpu_nvcsi_intr: tstamp:3925847774 class:GLOBAL type:STREAM_NOVC phy:0 cil:0 st:2 vc:0 status:0x00000001
[b]thank you，
I tried the solution：[/b]
Can try disable the ECC check.
diff --git a/drivers/media/platform/tegra/camera/csi/csi4_fops.c b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
index 0377d7b..b3d01d3 100644
--- a/drivers/media/platform/tegra/camera/csi/csi4_fops.c
+++ b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
@@ -76,8 +76,18 @@ static void csi4_stream_init(struct tegra_csi_channel *chan, int port_num)
csi4_stream_write(chan, port_num, INTR_STATUS, 0x3ffff);
csi4_stream_write(chan, port_num, ERR_INTR_STATUS, 0x7ffff);
csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK, 0x0);
- csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
- csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+
+ csi4_stream_write(chan, port_num, INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+ PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+ csi4_stream_write(chan, port_num, ERR_INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+ PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+ csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK,
+ CFG_ERR_STATUS2VI_MASK_VC0 |
+ CFG_ERR_STATUS2VI_MASK_VC1 |
+ CFG_ERR_STATUS2VI_MASK_VC2 |
+ CFG_ERR_STATUS2VI_MASK_VC3);
}
but it seems not work！
Besides!
Our hardware connection:
CSI2 is connectted by two video output, each has 1 data lane.
video 0 → csi2 lane0
video 1 → csi2 lane1
video 2 → csi3 lane0
video 3 → csi3 lane1
I only enabled 1 channel video0 currently, but can this solution work?
That patch is for TX2, You need to check if have the same REG for csi5_fops.c
Looks like not correct. Have a check the design guide and below like maybe help.
thanks for your reply，I removed the hardware connection：
video 0 → csi2 lane0
video 1 → csi2 lane1
video 2 → csi3 lane0
video 3 → csi3 lane1
And I got the different error log from trace， would you please help me to understand it:
kworker/0:0-4 [000] … 182.400274: rtcpu_nvcsi_intr: tstamp:5898103257 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x10000004
kworker/0:0-4 [000] … 182.400274: rtcpu_nvcsi_intr: tstamp:5898103257 class:CORRECTABLE_ERR type:PHY_INTR phy:1 cil:0 st:0 vc:0 status:0x00001004
kworker/0:0-4 [000] … 182.400274: rtcpu_nvcsi_intr: tstamp:5898103769 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000004
kworker/0:0-4 [000] … 182.400274: rtcpu_nvcsi_intr: tstamp:5898103769 class:CORRECTABLE_ERR type:PHY_INTR phy:1 cil:0 st:0 vc:0 status:0x00000004
kworker/0:0-4 [000] … 182.400275: rtcpu_nvcsi_intr: tstamp:5898104284 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x10000004
kworker/0:0-4 [000] … 182.400275: rtcpu_nvcsi_intr: tstamp:5898104284 class:CORRECTABLE_ERR type:PHY_INTR phy:1 cil:0 st:0 vc:0 status:0x00001004
kworker/0:0-4 [000] … 182.400275: rtcpu_nvcsi_intr: tstamp:5898104796 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x10000004
kworker/0:0-4 [000] … 182.400275: rtcpu_nvcsi_intr: tstamp:5898104796 class:CORRECTABLE_ERR type:PHY_INTR phy:1 cil:0 st:0 vc:0 status:0x00001004
kworker/0:0-4 [000] … 182.400275: rtcpu_nvcsi_intr: tstamp:5898105311 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x10000004
It could be the lane configure problem. Have a check the TRM for the REG “NVCSI_PHY_0_CILA_INTR_0_STATUS_CILA_0”
Make sure lane configure of the sensor and NVCSI are the same.
Could you give me a link to get information of REG “NVCSI_PHY_0_CILA_INTR_0_STATUS_CILA_0”?
And I think my configuration is correct, here is it:
vi@15c10000 {
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
nvp6324_vi_in0: endpoint {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&nvp6324_csi_out0>;
};
};
};
};
nvcsi@15a00000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
nvp6324_csi_in0: endpoint@0 {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&linvp6324_nvp6324_out0>;
};
};
port@1 {
reg = <1>;
nvp6324_csi_out0: endpoint@1 {
remote-endpoint = <&nvp6324_vi_in0>;
};
};
};
};
}
I found that I need to use the virtual channel tech, is there any example for virtual channel settings and driver writings?
Check the imx390 for VC support.
…/common/kernel-dts/t19x-common-modules/tegra194-camera-imx390-a00.dtsi
Hi @wangxiaopeng ,
Did your driver work ? I need to make a driver for the same device nvp6324.
regards.