I assume you’re referring to TRM section 7.4.
It looks like at the lowest level it’s simply register access via the TMR controller…see TRM page 20. Base physical address is shown as 6000:5000. First explanation starts in section 7.4. Actual controller information starts in section 7.10.1. This would provide full access to all timers.
You’re probably not looking to make it that difficult, so there is a possibility of some access via /sys to make life easier. The default R21.4 kernel config includes:
# CONFIG_TEGRA_WATCHDOG_ENABLE_ON_PROBE is not set
I don’t know what user space configuration is available for the Tegra watchdog, but there is some exposure in /sys. Observe:
# find /sys -name '*watchdog*'
(see also “find /sys -name ‘wdt’”)
The entry for /sys/class/misc/watchdog0 is a symbolic link which points to the /sys/devices/platform/tegra_wdt.0/misc/watchdog0 entry. Presumably this means the driver has configured watchdog 0 of core 0 for use. It may be possible to enable more watchdog timers for the other cores and access them via similar /sys entries, but it looks like code has not yet been written for watchdog1 through 3.
In the kernel source look at arch/arm/mach-tegra/board-ardbeg.c, which is of interest:
The reason this is “interesting” is because it ties directly to watchdog timer 0 via variable tegra_wdt0_device, and watchdog timer 0 is the one enabled and accessible via /sys in the default configuration. Grep through the rest of the kernel source does not show any occurrence of tegra_wdt#_device other than ‘#’ of ‘0’. You could probably track down the tegra_wdt0_device code and make similar code available as tegra_wdt1_device through tegra_wdt3_device and have full access via simple /sys interface (at least to the extent of the existing watchdog0 code).