What is the cache replacement policy in RNIC's SRAM cache (ConnectX3/4/5)? LRU, FIFO, or others?

RNIC caches PTE, PTT, WQE and QP states in its SRAM. However, when the number of connections increases, the above informations are more likely to be evicted out of the RNIC cache because the cache is small, and the RNIC has to read them back from memory when processing them. Then I have a question: What is the cache replacement policy in RNIC’s SRAM cache? LRU, FIFO, or others? Thank you! I look forward to your answer.

Hi Xuan,

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