Writel function had been CBB-FIREWALL_ERR

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
,
1

Hi guys:
I had custom board issues fixed in JetPack-5.0.1 with code in csi5_fops.csi5_power_on

// //NVCSI_PHY_0_NVCSI_CIL_A_PAD_CONFIG_0
	cila = 
		(0x01 << CSI5_E_INPUT_LP_IO1_SHIFT) |
		(0x01 << CSI5_E_INPUT_LP_IO0_SHIFT) |
		(0x00 << CSI5_E_INPUT_LP_CLK_SHIFT) |
		(0x01 << CSI5_PD_CLK_SHIFT) |
		(0x00 << CSI5_PD_IO1_SHIFT) |
		(0x00 << CSI5_PD_IO0_SHIFT);
	//NVCSI_PHY_0_NVCSI_CIL_B_PAD_CONFIG_0
	cilb = 
		(0x01 << CSI5_E_INPUT_LP_IO1_SHIFT) |
		(0x00 << CSI5_E_INPUT_LP_IO0_SHIFT) |
		(0x00 << CSI5_E_INPUT_LP_CLK_SHIFT) |
		(0x01 << CSI5_PD_CLK_SHIFT) |
		(0x00 << CSI5_PD_IO1_SHIFT) |
		(0x01 << CSI5_PD_IO0_SHIFT);
	writel(cila, ioremap(0x15a11c8c,4));//NVCSI_PHY_0_NVCSI_CIL_A_PAD_CONFIG
	writel(cilb, ioremap(0x15a11d8c,4));//NVCSI_PHY_0_NVCSI_CIL_B_PAD_CONFIG
	writel(cila, ioremap(0x15a21c8c,4));//NVCSI_PHY_1_NVCSI_CIL_A_PAD_CONFIG
	writel(cilb, ioremap(0x15a21d8c,4));//NVCSI_PHY_1_NVCSI_CIL_B_PAD_CONFIG
	writel(3, ioremap(0x15a11c7c,4));
	writel(3, ioremap(0x15a11d7c,4));
	writel(3, ioremap(0x15a21c7c,4));
	writel(3, ioremap(0x15a21d7c,4));

It’s working on Jetpack 5.0.1 but Not work on Jetpack 5.0.2

[   86.358697] CPU:0, Error:cbb-fabric@0x13a00000, irq=21
[   86.358706] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_power_on readl CILA CONFIG 0xffffffff
[   86.364006] **************************************
[   86.364008] CPU:0, Error:cbb-fabric, Errmon:2
[   86.364014]    Error Code            : FIREWALL_ERR
[   86.364015]    Overflow              : Multiple FIREWALL_ERR

[   86.368979] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_power_on readl CILB CONFIG 0xffffffff
[   86.373446]    Error Code            : FIREWALL_ERR
[   86.373449]    MASTER_ID             : CCPLEX
[   86.373450]    Address               : 0x15a11c8c
[   86.373452]    Cache                 : 0x1 -- Bufferable
[   86.373457]    Protection            : 0x2 -- Unprivileged, Non-Secure, Data Access
[   86.377596] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_power_on readl CILA CONFIG 0xffffffff
[   86.382341]    Access_Type           : Write
[   86.382342]    Access_ID             : 0x7
[   86.382344]    Fabric                : cbb-fabric
[   86.382346]    Slave_Id              : 0x3
[   86.383884] t194-nvcsi 13e40000.host1x:nvcsi@15a00000: csi5_power_on readl CILB CONFIG 0xffffffff
[   86.388012]    Burst_length          : 0x0
[   86.388013]    Burst_type            : 0x1
[   86.388014]    Beat_size             : 0x2
[   86.388016]    VQC                   : 0x0
[   86.388019]    GRPSEC                : 0x7e
[   86.435904]    FALCONSEC             : 0x0
[   86.439128]    Slave                 : T234_CBB_SN_HOST1X
[   86.443429]  **************************************
[   86.448460] ------------[ cut here ]------------

Is Any Replacement command for writel()?

3

hello mnbhjk3,

may I know what’s the actual use-case for writing CIL directly?

4

I had custom board to connection with sensor, but hardware layout need for CPHY Trio1/2/3 to Trio1/2/4

5

hello mnbhjk3,

I don’t understand this part, isn’t it a 3-lane configuration.
could you please refer to Camera Module Hardware Design Guide. thanks

6

Hi JerryChang:
My hardware guy said Trio 1/2/4 is easy to layout.
So I couldn’t writing CIL anymore in JetPack 5.0.2?

7

hello mnbhjk3,

FYI,
we see an issue on JetPack-5.0.2, it shows error when accessing NVCSI registers.
this seems only repo’ed on AGX Orin platforms, we see validate data on AGX Xavier series.

8

hello mnbhjk3,

please also describe what’s the issues fixed by register writes.
don’t you detect all 3 cphy sensors with correct device tree configurations?

9

Hi JerryChange:
please also describe what’s the issues fixed by register writes. —> Turn off Trio3 & Power Down Trio3
don’t you detect all 3 cphy sensors with correct device tree configurations? → No, because HW connection is not usual connect I describe below

Our hardware guy connect C-PHY 3-Trio on Orin&Xavier with Trio1/2/4 on NVCSI.
HW layout look like:

Our Sensor | Jetson Orin
Trio1 -------->Trio1    //Connect
Trio2 -------->Trio2 //Connect
Empty -------->Trio3  // Not connect
Trio3 -------->Trio4 //Connect

So I Tune off Trio3 & Power down Trio3 with reg

//NVCSI_PHY_0_NVCSI_CIL_A_PAD_CONFIG_0
	cila = 
		(0x01 << CSI5_E_INPUT_LP_IO1_SHIFT) |  //Trio 2 enable
		(0x01 << CSI5_E_INPUT_LP_IO0_SHIFT) | //Trio 1 enable
		(0x00 << CSI5_E_INPUT_LP_CLK_SHIFT) |  // not used for CPHY
		(0x01 << CSI5_PD_CLK_SHIFT) |  // not used for CPHY
		(0x00 << CSI5_PD_IO1_SHIFT) |  //power on Trio2
		(0x00 << CSI5_PD_IO0_SHIFT);  // power on Trio1
	//NVCSI_PHY_0_NVCSI_CIL_B_PAD_CONFIG_0
	cilb = 
		(0x01 << CSI5_E_INPUT_LP_IO1_SHIFT) | // Trio 4 enable
		(0x00 << CSI5_E_INPUT_LP_IO0_SHIFT) | // Trio 3 disable
		(0x00 << CSI5_E_INPUT_LP_CLK_SHIFT) | //not used for CPHY
		(0x01 << CSI5_PD_CLK_SHIFT) |  //not used for CPHY
		(0x00 << CSI5_PD_IO1_SHIFT) |  // Power on  Trio4 
		(0x01 << CSI5_PD_IO0_SHIFT);  // Power off Trio3  

        writel(cila, ioremap(0x15a11c8c,4));//NVCSI_PHY_0_NVCSI_CIL_A_PAD_CONFIG     Write into reg(NVCSI CH1)
	writel(cilb, ioremap(0x15a11d8c,4));//NVCSI_PHY_0_NVCSI_CIL_B_PAD_CONFIG   
	writel(cila, ioremap(0x15a21c8c,4));//NVCSI_PHY_1_NVCSI_CIL_A_PAD_CONFIG   Write into reg(NVCSI CH2)
	writel(cilb, ioremap(0x15a21d8c,4));//NVCSI_PHY_1_NVCSI_CIL_B_PAD_CONFIG
	writel(3, ioremap(0x15a11c7c,4));    //With 3 Trio for CPHY CH1-CILA
	writel(3, ioremap(0x15a11d7c,4));    //With 3 Trio for CPHY CH1-CILB
	writel(3, ioremap(0x15a21c7c,4));    //With 3 Trio for CPHY CH2-CILA
	writel(3, ioremap(0x15a21d7c,4));    //With 3 Trio for CPHY CH2-CILB

[/quote]

10

hello mnbhjk3,

may I know what’s your device tree settings. I don’t think you’ll need to disable Trio3 with correct settings.

note.
here’re 4 bricks and you should note it’s first two brick to have dual streams.
for example,

CPHY CSI brick VI stream
Trio1 CSI-A/B Stream-0, 1
Trio2 CSI-C/D Stream-2, 3
Trio3 CSI-E/F Stream-4
Trio4 CSI-G/H Stream-5
12

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.