We’re looking at migrating a design from TX2 to Xavier NX. We have some regulators on our carrier board which we need to configure by I2C before booting Linux. On TX2, this was working just fine via tweaking the MB1 PMIC BCT configuration. On Xavier NX, this is not working. We are using module signals I2C1_SCL/I2C1_SDA (pins 189, 191) on Xavier NX aka. I2C9 on the Xavier SoC.
Specifying this in the Xavier NX MB1 PMIC BCT configuration:
pmic.system.block.type = 1; # I2C Type pmic.system.block.controller-id = 8; pmic.system.block.slave-add = 0x4A; pmic.system.block.reg-data-size = 8; pmic.system.block.reg-add-size = 8; pmic.system.block.block-delay = 10; pmic.system.block.commands.0x01.0xFF = 0xFF; pmic.system.block.commands.0x03.0xFF = 0x00;
Results in this error message:
[0080.079] E> MB1_PLATFORM_CONFIG: Invalid value ctrl_id: 8. [0080.085] C> NONE: Failed to update reg address 0x01 of slave 0x4a in i2c bl.
So, it looks like MB1 does not support doing anything on I2C9. I thought I should try adjusting CBoot; I added the following code to CBoot:
struct tegrabl_i2c_dev *hi2c = tegrabl_i2c_dev_open(TEGRABL_INSTANCE_I2C9, 0x4A, 1, 1);
However, the board just hangs during boot when it is trying to write to the DPAUX3 registers in the SoC. My guess is that something has not been taken out of reset or remains unpowered, although it looks like
tegrabl_dpaux.c makes an attempt to configure things and take them out of reset. What are the clock tree dependencies for DPAUX3? Does SOR3 have to be configured and running in order for access to DPAUX3 to work? Is there a PLL dependency? Can you provide a method for MB1 or CBoot to be able to successfully write I2C registers on I2C9?