@ShaneCCC
Could you try send more packet?
if yo send just one package, maybe no errors.
try command as follows, let -n=-1(infinite loop):
for slave: sudo ./spidev_test -D /dev/spidev0.0 -s5000000 -g884 -b8 -p0 -n-1 -r
for master: sudo ./spidev_test -D /dev/spidev0.0 -s5000000 -g884-b8 -p0 -n-1 -zzz -t
I try -s11000000 -g4096 without problem. But -s5000000 will got the problem.
@ShaneCCC
-s11000000 without jetson_clock?
how about -s10000000?
Yes without jetson_clocks, looks like only 11000000 without problem.
I have try -s11000000 -g4096 without jetson_clocks and no good.
Did you run two jetson device loopback test?
@ShaneCCC
Yes, two jetson xavier device, one master, one slave, both use spi0.
I configure the spi2 as slave.
@ShaneCCC
Is there any difference between spi1 and spi2?
How to make spi1 working as slave?
What was the reason for spi1 not work properly? soc HW bug? or anything else?
thanks
Suppose should be doesn’t have any different. I just use the default device tree configure to try it for convenience.
I would suggest to reduce the transfer package to check if still have the problem.
Current had report your problem to internal developer to seek if any suggestion to you. Once get update will update here.
Thanks
update:
slave: sudo ./spidev_test -D /dev/spidev0.0 -s1000000 -g512 -b8 -p0 -n-1 -r -zzz
master: sudo ./spidev_test -D /dev/spidev0.0 -s1000000 -g512 -b8 -p0 -n-1 -zzz -t
[ 563.478192] spi_master spi0: @isr
[ 563.478241] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0200]:RDY I:255 B:512
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.478359] spi-tegra124-slave 3210000.spi: rx-dma-complete
[ 563.478436] spi-tegra124-slave 3210000.spi: Profile: size=512B time-from-spi-int=159232ns
[ 563.479798] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.479824] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.479845] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.479875] spi_master spi0: Before DMA EN
[ 563.479899] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0200]:BSY I:255 B:512
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.483394] spi_master spi0: @isr
[ 563.483426] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0192]:RDY I:255 B:402
FIFO[82c00004]:RxF:5 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.483707] tegra_spi_wait_on_message_xfer: 2 callbacks suppressed
[ 563.483716] spi_master spi0: transferred[402] != requested[512]
[ 563.484003] tegra_spi_wait_on_message_xfer: 2 callbacks suppressed
[ 563.484021] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0192]:BSY I:255 B:402
FIFO[02c00004]:RxF:5 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.484638] handle_dma_based_err_xfer: 2 callbacks suppressed
[ 563.484643] spi_master spi0: rx-dma-err [status:82c00004]
[ 563.484870] handle_dma_based_err_xfer: 2 callbacks suppressed
[ 563.484885] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[02c00004]:RxF:5 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.485400] spi_master spi0: failed to transfer one message from queue
[ 563.486300] spi_master spi0: after controller reset
[ 563.486322] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 563.486335] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.486387] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.486406] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.486435] spi_master spi0: Before DMA EN
[ 563.486452] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.488430] spi_master spi0: @isr
[ 563.488444] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff00d7]:RDY I:255 B:215
FIFO[83400004]:RxF:6 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.488489] spi_master spi0: transferred[215] != requested[512]
[ 563.488645] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff00d7]:BSY I:255 B:215
FIFO[03400004]:RxF:6 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.498440] spi_master spi0: rx-dma-err [status:83400004]
[ 563.503994] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[03400004]:RxF:6 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.523291] spi_master spi0: failed to transfer one message from queue
[ 563.530017] spi_master spi0: after controller reset
[ 563.530029] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 563.530036] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.530049] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.530060] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.530077] spi_master spi0: Before DMA EN
[ 563.530086] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.531836] spi_master spi0: @isr
[ 563.531852] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff00c3]:RDY I:255 B:195
FIFO[80c00004]:RxF:1 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.531885] spi_master spi0: transferred[195] != requested[512]
[ 563.535680] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff00c3]:BSY I:255 B:195
FIFO[00c00004]:RxF:1 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.555298] spi_master spi0: rx-dma-err [status:80c00004]
[ 563.560613] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00c00004]:RxF:1 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.579816] spi_master spi0: failed to transfer one message from queue
[ 563.592213] spi_master spi0: after controller reset
[ 563.592237] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 563.592248] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.592267] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.592283] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.592306] spi_master spi0: Before DMA EN
[ 563.592323] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.595107] spi_master spi0: @isr
[ 563.595137] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff013b]:RDY I:255 B:315
FIFO[83c00004]:RxF:7 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.595301] spi_master spi0: transferred[315] != requested[512]
[ 563.595504] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff013b]:BSY I:255 B:315
FIFO[03c00004]:RxF:7 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.611980] spi_master spi0: rx-dma-err [status:83c00004]
[ 563.617689] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[03c00004]:RxF:7 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.636922] spi_master spi0: failed to transfer one message from queue
[ 563.643685] spi_master spi0: after controller reset
[ 563.643703] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 563.643712] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.643727] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.643738] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.643756] spi_master spi0: Before DMA EN
[ 563.643784] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.645367] spi_master spi0: @isr
[ 563.645387] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff00b1]:RDY I:255 B:177
FIFO[82400004]:RxF:4 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.645452] spi_master spi0: transferred[177] != requested[512]
[ 563.648988] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff00b1]:BSY I:255 B:177
FIFO[02400004]:RxF:4 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.668916] spi_master spi0: rx-dma-err [status:82400004]
[ 563.674433] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[02400004]:RxF:4 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.693634] spi_master spi0: failed to transfer one message from queue
[ 563.706280] spi_master spi0: after controller reset
[ 563.706298] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 563.706306] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.706320] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.706331] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.706349] spi_master spi0: Before DMA EN
[ 563.706360] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.706580] spi_master spi0: @isr
[ 563.706596] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff000e]:RDY I:255 B:14
FIFO[82400004]:RxF:4 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.706626] spi_master spi0: transferred[14] != requested[512]
[ 563.706770] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff000e]:BSY I:255 B:14
FIFO[02400004]:RxF:4 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.725182] spi_master spi0: rx-dma-err [status:82400004]
[ 563.730972] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[02400004]:RxF:4 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.749903] spi_master spi0: failed to transfer one message from queue
[ 563.762900] spi_master spi0: after controller reset
[ 563.762923] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 563.762934] spi-tegra124-slave 3210000.spi: Rx len:512 bpw:8 0us 1000000Hz
[ 563.762958] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 563.762973] spi-tegra124-slave 3210000.spi: Starting rx dma for len:512
[ 563.762995] spi_master spi0: Before DMA EN
[ 563.763011] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:511
[ 563.767867] spi_master spi0: @isr
After run jetson_clocks, error may reduce a lot.
I noticed the error as follows:
FIFO[82400004]:RxF:4 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]:
the CS input signal looks good
Please verify this patch.
Thanks
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 9a4abb4..2aadf42 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -1490,10 +1490,8 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
msg->actual_length += xfer->len;
complete_xfer:
- if (prefer_last_used_cs)
cmd1 = tspi->command1_reg;
- else
- cmd1 = tspi->def_command1_reg;
+
if (ret < 0 || skip) {
if (cstate && cstate->cs_gpio_valid)
gpio_set_value(spi->cs_gpio, gval);
@ShaneCCC
I have verified thid patch, but no good.
log as follows:
[ 166.393251] spi_master spi0: @isr
[ 166.393303] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff1000]:RDY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.393411] spi-tegra124-slave 3210000.spi: rx-dma-complete
[ 166.394446] spi-tegra124-slave 3210000.spi: Profile: size=4096B time-from-spi-int=1102528ns
[ 166.422601] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.422619] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.422634] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.422653] spi_master spi0: Before DMA EN
[ 166.422665] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff1000]:BSY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.430320] spi_master spi0: @isr
[ 166.430356] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0385]:RDY I:255 B:901
FIFO[81400004]:RxF:2 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.431599] spi_master spi0: transferred[901] != requested[4096]
[ 166.431784] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0385]:BSY I:255 B:901
FIFO[01400004]:RxF:2 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.432236] spi_master spi0: rx-dma-err [status:81400004]
[ 166.432359] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0385]:BSY I:255 B:901
FIFO[01400004]:RxF:2 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.432756] spi_master spi0: failed to transfer one message from queue
[ 166.435048] spi_master spi0: after controller reset
[ 166.435081] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 166.435096] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.435115] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.435130] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.435167] spi_master spi0: Before DMA EN
[ 166.435179] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.467285] spi_master spi0: @isr
[ 166.467316] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0efb]:RDY I:255 B:3835
FIFO[83c00004]:RxF:7 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.468005] spi_master spi0: transferred[3835] != requested[4096]
[ 166.468250] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0efb]:BSY I:255 B:3835
FIFO[03c00004]:RxF:7 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.468626] spi_master spi0: rx-dma-err [status:83c00004]
[ 166.468748] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0efb]:BSY I:255 B:3835
FIFO[03c00004]:RxF:7 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.469285] spi_master spi0: failed to transfer one message from queue
[ 166.469898] spi_master spi0: after controller reset
[ 166.469925] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 166.469938] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.470020] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.470038] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.470065] spi_master spi0: Before DMA EN
[ 166.470082] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.506161] spi_master spi0: @isr
[ 166.506193] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff1000]:RDY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.506280] spi-tegra124-slave 3210000.spi: rx-dma-complete
[ 166.506581] spi-tegra124-slave 3210000.spi: Profile: size=4096B time-from-spi-int=364640ns
[ 166.529792] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.529827] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.529848] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.529884] spi_master spi0: Before DMA EN
[ 166.529907] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.545388] spi_master spi0: @isr
[ 166.545424] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0730]:RDY I:255 B:1840
FIFO[82400004]:RxF:4 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.545556] spi_master spi0: transferred[1840] != requested[4096]
[ 166.545737] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0730]:BSY I:255 B:1840
FIFO[02400004]:RxF:4 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.546146] spi_master spi0: rx-dma-err [status:82400004]
[ 166.546272] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0730]:BSY I:255 B:1840
FIFO[02400004]:RxF:4 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.546828] spi_master spi0: failed to transfer one message from queue
[ 166.548733] spi_master spi0: after controller reset
[ 166.548758] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 166.548774] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.548792] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.548807] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.548834] spi_master spi0: Before DMA EN
[ 166.548851] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.584224] spi_master spi0: @isr
[ 166.584254] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff1000]:RDY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.584333] spi-tegra124-slave 3210000.spi: rx-dma-complete
[ 166.584405] spi-tegra124-slave 3210000.spi: Profile: size=4096B time-from-spi-int=122304ns
[ 166.612566] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.612595] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.612615] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.612646] spi_master spi0: Before DMA EN
[ 166.612670] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.623761] spi_master spi0: @isr
[ 166.623795] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0515]:RDY I:255 B:1301
FIFO[83400004]:RxF:6 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.623885] spi_master spi0: transferred[1301] != requested[4096]
[ 166.624066] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0515]:BSY I:255 B:1301
FIFO[03400004]:RxF:6 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.624422] spi_master spi0: rx-dma-err [status:83400004]
[ 166.624536] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0515]:BSY I:255 B:1301
FIFO[03400004]:RxF:6 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.624963] spi_master spi0: failed to transfer one message from queue
[ 166.625570] spi_master spi0: after controller reset
[ 166.625593] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 166.625605] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.625628] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.625644] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.625670] spi_master spi0: Before DMA EN
[ 166.625687] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.662906] spi_master spi0: @isr
[ 166.662936] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff1000]:RDY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.663026] spi-tegra124-slave 3210000.spi: rx-dma-complete
[ 166.663384] spi-tegra124-slave 3210000.spi: Profile: size=4096B time-from-spi-int=423296ns
[ 166.681167] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.681184] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.681196] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.681213] spi_master spi0: Before DMA EN
[ 166.681224] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff1000]:BSY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.701845] spi_master spi0: @isr
[ 166.701882] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff0996]:RDY I:255 B:2454
FIFO[83400004]:RxF:6 TxE:64 Err[Cs] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.701955] spi_master spi0: transferred[2454] != requested[4096]
[ 166.702133] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0996]:BSY I:255 B:2454
FIFO[03400004]:RxF:6 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.702639] spi_master spi0: rx-dma-err [status:83400004]
[ 166.702768] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0996]:BSY I:255 B:2454
FIFO[03400004]:RxF:6 TxE:64 Err[] RxSTA[] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.703245] spi_master spi0: failed to transfer one message from queue
[ 166.703844] spi_master spi0: after controller reset
[ 166.703885] spi_master spi0: CMD[13f00000]: Sl M1 CS0 [HHHH] MSB MSb Un 1b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:0
[ 166.703905] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.703928] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.703948] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.703976] spi_master spi0: Before DMA EN
[ 166.703993] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff0000]:BSY I:255 B:0
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.740614] spi_master spi0: @isr
[ 166.740667] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[40ff1000]:RDY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
[ 166.740750] spi-tegra124-slave 3210000.spi: rx-dma-complete
[ 166.740824] spi-tegra124-slave 3210000.spi: Profile: size=4096B time-from-spi-int=130048ns
[ 166.766327] spi-tegra124-slave 3210000.spi: Rx len:4096 bpw:8 0us 1000000Hz
[ 166.766368] spi-tegra124-slave 3210000.spi: The def 0x13f00000 and written 0x3f01027
[ 166.766393] spi-tegra124-slave 3210000.spi: Starting rx dma for len:4096
[ 166.766428] spi_master spi0: Before DMA EN
[ 166.766657] spi_master spi0: CMD[03f01027]: Sl M0 CS0 [HHHH] MSB MSb Rx Pa 8b TRANS[00ff1000]:BSY I:255 B:4096
FIFO[00400005]:RxF:0 TxE:64 Err[] RxSTA[E] TxSTA[E]DMA[00110000]: RxTr:2 TxTr:2 B:4095
@ShaneCCC
Any luck with this case for so long?
@cloundliu
Please add nvidia,variable-length-transfer in the controller data and try
controller-data {
nvidia,variable-length-transfer;
};
@ShaneCCC
I have added this in the controller data before and useless.
Just avoid errors reporting and you will lost data, because you can’t receive the fixed length of data you set on one transfer.
What kind of condition will lost data?
@ShaneCCC
Lost data as before, Err[Cs] error remains.