Xavier USB Port Routing



The Xavier TRM 1.4p says this about USB 3.1 Ports:

TRM USB 3.1 Ports 

USB 3.1 ports support both Generation 1 SuperSpeed USB and Generation 2 SuperSpeedPlus 
USB 10 Gbps transfer rates. 

Note that due to throughput limitations in the xHCI controller, USB 3.1 port 0 and port 3 are 
connected to the same SuperSpeedPlus hub to share 10 Gbps total bandwidth, while 
USB 3.1 port 1 and port 2 share another 10 Gbps total bandwidth. Note also that in the case of
two SuperSpeed devices connected to the same SuperSpeedPlus hub, due to scheduling policy
reasons each SuperSpeed device may not be able sustain the full SuperSpeed unit bandwidth
if the other is device is active. 

TRM Photo
Figure 9.3

This photo makes it look like P0 and P1 are attached to the same SuperSpeedPlus hub, and then
P2 and P3 are attached to a different SuperSpeedPlus hub, which conflicts with TRM documentation.
The area in the “XUSBA” box is what convinced us that P0+P1 shared a USB hub and P2+P3 shared the other USB hub.

This is a problem because we have our own carrier board and wired USB ports P0 and P1 together
to a series of high bandwidth devices instead of wiring P0+P3 together… and we are seeing
bandwidth issues.

Xavier Data Sheet USB 3.1 (Host) Operation  

USB 3.1 ports support both Generation 1 - SuperSpeed USB and Generation 2 - SuperSpeed USB
10Gbps transfer rates. USB 3.1 port 0 and port 3 share one 10Gbps  unit bandwidth, while USB
3.1 is allocated a separate 10Gbps unit bandwidth.  All USB 3.1 ports support hardware initiated
U1 and U2 link power management as well as software initiate U3 (suspend) link power

Which Xavier USB wiring information is correct? The TRM text and datasheet text or the TRM diagram?

Thank you,


It should be the description in word that Port 0 and 3 share same bandwidth, and so port 1 and 2. Figure 9.3 doesn’t mean what you say, it doesn’t show different bandwidth, and as you can see, it list the ports in turn as P2, P1, P0, P3.

Figure 9.3 shows the section below and appears to show “P2” and “P3” being wired together and feeding into the xHCI Controller. Similarly, P0 and P1 appear to be wired together and feeding into the xHCI controller. That is what I see and how I interpret the diagram.

I’m not sure how to interpret the the order of the ports and how that might affect downstream bandwidth?


We were confused by this because, to us, this part of the diagram appears to have USB3 Port 2 and Port 3 connected on the same hub and USB3 Port 0 and Port 1 sharing the same hub (but different hub from Port 2 and Port 3).


Please refer to the description that P0 and P3 share same bandwidth, P1 and P2 share same bandwidth. We will check if this figure needs to be optimized.