I want to establish dma transaction of 4K size frames between Jetson & FPGA using the Xilinx DMA engine running on the FPGA.
I am able to do the dma transaction in non-cyclic mode with the driver source provided in this link,
These are the steps followed in setting up environment from the above link ( in our case Jetpack 4.2.2 is used ):
Install Jetpack 2.3.1 (L4T 24.2.1)
Unpack L4T 24.2.1 kernel to TX1 and compile/install using jetsonhacks build script
Download Xilinx XDMA driver sources (https://www.xilinx.com/Attachment/Xilinx_Answer_65444_Linux_Files.zip)
Unpack Xilinx XDMA sources to /home/nvidia
Modify RX_BUF_PAGES in Xilinx driver include/xdma-core.h from 256 to 2048
Download version of Xilinx xdma_core.c file with cyclic buffer disabled
Apply the attached patch
Build Xilinx XDMA sources and run load_driver.sh with FPGA plugged into PCIe and programmed with loopback design
At this point, multiple transfers of size 8M will complete without data errors, but dmesg will still show mc-errs and smmu faults.