40-pin Expansion Header pin8 and pin10 - UART

Hi, I am having trouble understanding the UART layout of Xavier NX in both the hardware and software level.

As per my understanding, there are 3 UARTs available on Xavier NX. According to Figure 11-5 (JetsonXavier NX UART Connections) in NVIDIA Jetson Xavier NX Developer Kit Carrier Board P3509_A01, the 3 UARTs are:

  1. SoC: UART2 = Jetson: UART0 ttyTHS0: for internal use, M.2 Key E
  2. SoC: UART1 = Jetson: UART1 ttyTHS1: for general use, UART General
  3. SoC: UART3 = Jetson: UART2 ttyTHS4: for debugging, Debug UART

Naturally, I traced UART1_TXD (203) and UART1_RXD (205) to pin8 and pin10 on the Dev Kit’s 40-pin Expansion Header (Figure 3-1) to connect with this other hardware. Additionally, I ensured the connection is correct, i.e. cross-connected between the hardware, and pin8 and pin10 on the Xavier NX - TX to RX and RX to TX, GND to GND. In the system level, I initiated the communication through ttyTHS1 but there is no communication in that port… Then I did a simple loop back test to make sure on the hardware level, pins are working. But the communication was unsuccessful… After that, I decided to try out the other 2 UART ports and ttyTHS0 turned out to be the right port and communication was successful both for the loop back test and communication with the hardware.

While I did not customize the DTS, my assumption is that my default Xavier NX is mapped to be:

  1. Jetson: UART1 ttyTHS1: for internal use, M.2 Key E
  2. Jetson: UART0 ttyTHS0: for general use, UART General
  3. Jetson: UART2 ttyTHS4: for debugging, Debug UART
    However, I am not sure how to confirm this. At least from the trial and error process I just described, I was able to communicate through ttyTHS0 and not ttyTHS1 on pin8 and pin10.

Then, I started looking deeper into my Xavier NX port configuration but I didn’t go far as I don’t fully comprehend (hence asking for help here)… Through the developer guide, I found another documentation about Configuring the 40-Pin Expansion Header, and in the Xavier NX terminal I launched the Jetson-IO $ sudo /opt/nvidia/jetson-io/jetson-io.py. It appears that my header configuration is a bit different from the documentation (find attached photos).

image

Pin8 and pin10 on my Xavier NX is uartabut documentation is uartb. Could this be the root cause of my problem? Additionally, I am not an expert in EE, could someone please explain how is uarta and uartb related to the UART on SoC level, Jetson level and IO level. Please advise. Thank you very much.

hello anthony.yan,

you may search for kernel init messages for the register serial ports.
for example,

$ dmesg | grep THS
[    1.487558] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 47, base_baud = 0) is a TEGRA_UART
[    1.488728] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 48, base_baud = 0) is a TEGRA_UART
[    1.489472] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 49, base_baud = 0) is a TEGRA_UART

here’s device tree to show the UART port for these address.
for example,
$L4T_Sources/r32.5/Linux_for_Tegra/source/public/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-uart.dtsi

        uarta: serial@3100000 {
        uartb: serial@3110000 {
        uarte: serial@3140000 {

Hi JerryChang,

Thank you for the response. My Xavier NX reflects the same configurations as you suggested:

$ dmesg | grep THS
[    1.424639] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 47, base_baud = 0) is a TEGRA_UART
[    1.425706] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 48, base_baud = 0) is a TEGRA_UART
[    1.426569] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 49, base_baud = 0) is a TEGRA_UART

My follow up questions are below:

  1. Is this configuration the default UART configuration?

  2. Is the new configuration like this:

    1. SoC: UART1 = Jetson: UART1 ttyTHS0: for general use, UART General
    2. SoC: UART2 = Jetson: UART0 ttyTHS1: for internal use (not available to user), M.2 Key E
    3. SoC: UART3 = Jetson: UART2 ttyTHS4: for debugging, Debug UART
  3. Please explain a little bit more how and why UART is defined (differently?) in SoC, Jetson, and IO level.

  4. If I would like to change the configuration, is Jetson-IO $ sudo /opt/nvidia/jetson-io/jetson-io.py the only way?

Thank you.

hello anthony.yan,

there’re 3 UARTs available Jetson Xavier NX, UART0 to M2; UART1 to 40PIN; UART2 to debug.
you may also refer to Jetson Xavier NX Product Design Guide to check UART connections.
please also check similar discussion threads, such as Topic 149346, Topic 163766, and Topic 169692,
thanks