about mipi-csi lane speed

from the file drivers/media/platform/tegra/camera/csi/csi4_fops.c,I found TEGRA_CSICIL_CLK_MHZ which equals 204Mhz .

[b]Does it means the lane speed of tx2'csi is 204Mhz ?  Or can I modify it ?


I found the csi_settletime and cil_settletime have relationship with TEGRA_CSICIL_CLK_MHZ.

from the "mipi alliance specification for d-phy",page 54,we know that the Tclk-settle should be 

smaller than 300ns,and bigger than 95ns.but in nvidia’s code ,the result is :
csi_settletime: 33ns, cil_settletime: 25ns

It’s VI logic speed not the lane speed. The lane speed is as MIPI spec 1.5G.

you means the mipi-csi lane speed will always be 1.5G?

the mipi-csi module has master(transmitter) and slave(receiver). the frequency of salve is 1.5G,and the

1.5G will suitable for any frequency of master?

and,could you tell me where can I find the Tlpx of slave(receiver,tx2)? At mipi alliance specification

for d-phy ,page 55,there is a parameter: Ratio Tlpx . The description of this parameter is: Ratio of

Tlpx(master)/Tlpx(slave) between master and slave side. And the value should be smaller than 3/2 and

bigger than 2/3.

The Tlpx of master(tx358748xbg) is 68.57ns.

Hi, please check the “D-PHY Timing Values” table in TRM for Tlpx, also you can get other info of d-phy in TRM.