AGX orin connects to M.2 NVME SSD Tx/Rx

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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ORIN TX+RX
ORIN TX+RX854×553 52 KB

SSD TX+RX
SSD TX+RX1436×362 65.2 KB

cap
cap1351×346 66.5 KB

Hello,
1, Being Confusion on the PCIe connections to SSD in the reference design “P3737_A04_OrCAD_schematics.pdf”. In my understanding the PCIe connections should be ORIN Tx ↔ SSD RX, and ORIN Rx ↔ SSD Tx, however the reference design is different from my understanding, it has the following connections, ORIN Tx ↔ SSD TX, and ORIN Rx ↔ SSD Rx. Could you help to explain it?
2, I found a 0.22uF cap is placed close to each of SSD TX lines, but there are no caps placed on both ends of the RX lines. I think it should be TX signals on ORIN in opposite of the RX signals on SSD. Shall I keep no Rx caps as reference design or, add caps close to the ORIN/or the SSD?

6

Since the Jetson AGX Orin Carrier board is the host, B15 and B14 are the TX lines from the CPU’s perspective, which connect to the RX pins on the PCIe card.

For the capacitors, the PCIe standard requires AC coupling caps on the TX side. Therefore, the “missing” caps for the Orin’s RX lines should be placed on the PCIe card’s TX side.

7

Hi,
Thanks for reply.
Yes the Orin Carrier board is the host, the Tx on CPU should be routed to the Rx on PCIE card, however it shows otherwise in the reference design doc, the Tx on CPU is routed to the Tx on PCIE card instead. It works after all. But why it works at this connections?

TX-conn
TX-conn453×142 20.1 KB

8

Hi,

Hi, The PCIe edge connector on the DevKit uses system-side signal naming, so CPU TX is connected to the connector’s TX pin. When a PCIe card (or M.2 NVMe SSD) is plugged into the connector, the connector’s TX pin naturally routes to the card’s RX pin.

CPU (signal TX) ← PCB → Connector (naming TX) ↔ Connector (naming TX) ← PCB → Endpoint Device (signal RX).

Please let me know if that is still unclear.

9

Ok, got it.