AGX ORIN PCIE (C4) Lane Reverse?

[yoonju]

hello I have Some Question About AGX Orin PCIe I/F

The connected PCIE signals of M.2 KEY-M on AGX ORIN Dev Kit are connected as follows:

AGX ORIN ↔ M.2 KEY-M

1. UPHY_TX/RX[22] ↔ M.2 TX/RX[3]
2. UPHY_TX/RX[23] ↔ M.2 TX/RX[2]
3. UPHY_TX/RX[10] ↔ M.2 TX/RX[1]
4. UPHY_TX/RX[11] ↔ M.2 TX/RX[0]

As above, the lane is connected in reverse, but
I want to connect the carrier board that I am developing without reverse, as shown below.
AGX ORIN ↔ M.2 KEY-M

1. UPHY_TX/RX[22] ↔ M.2 TX/RX[0]
2. UPHY_TX/RX[23] ↔ M.2 TX/RX[1]
3. UPHY_TX/RX[10] ↔ M.2 TX/RX[2]
4. UPHY_TX/RX[11] ↔ M.2 TX/RX[3]

Will it work normally automatically even if I connect it like this without reverse?

• Is there something that needs to be processed in software? (EX: BSP)

[TomNVIDIA]

Hello,

Thanks for visiting the NVIDIA Developer forums! Your topic will be best served in the Jetson category.

I have moved this post for better visibility.

Cheers,
Tom

[sgursal]

PCIe lane reversal as you have proposed here in reverse order is supported. Expected to work as is.

[yoonju]

Thank you Everyone!