AGX Orin GMSL PORT

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
1

Hello,
I am currently porting a GMSL camera to the NVIDIA AGX Orin.
Below is the system structure I intend to implement.

image
image521×814 112 KB

Also, I would like to ask which port number is correct in the diagram below.
Could you please let me know whether the left side or the right side is correct?
image
image1173×1061 130 KB

Also, regarding DTS configuration,
what should I configure if I want to set the port-index field to a specific value?

I have confirmed that ports A and B correspond to port-index 0 and 1, respectively.

I searched through the source code, but I couldn’t find any references to G port or H port.
What should I do in this case?
+++++++++++++++++++++++ search result ++++++++++++++++++++++++++++++++
SOURCE/nvidia-oot/include/media/gmsl-link.h:29:define GMSL_CSI_PORT_A 0x0
SOURCE/nvidia-oot/include/media/gmsl-link.h:30:define GMSL_CSI_PORT_B 0x1
SOURCE/nvidia-oot/include/media/gmsl-link.h:31:define GMSL_CSI_PORT_C 0x2
SOURCE/nvidia-oot/include/media/gmsl-link.h:32:define GMSL_CSI_PORT_D 0x3
SOURCE/nvidia-oot/include/media/gmsl-link.h:33:define GMSL_CSI_PORT_E 0x4
SOURCE/nvidia-oot/include/media/gmsl-link.h:34:define GMSL_CSI_PORT_F 0x5
SOURCE/out/nvidia-linux-header/include/media/gmsl-link.h:29:define GMSL_CSI_PORT_A 0x0
SOURCE/out/nvidia-linux-header/include/media/gmsl-link.h:30:define GMSL_CSI_PORT_B 0x1
SOURCE/out/nvidia-linux-header/include/media/gmsl-link.h:31:define GMSL_CSI_PORT_C 0x2
SOURCE/out/nvidia-linux-header/include/media/gmsl-link.h:32:define GMSL_CSI_PORT_D 0x3
SOURCE/out/nvidia-linux-header/include/media/gmsl-link.h:33:define GMSL_CSI_PORT_E 0x4
SOURCE/out/nvidia-linux-header/include/media/gmsl-link.h:34:define GMSL_CSI_PORT_F 0x5
AGX/Linux_for_Tegra/rootfs/usr/src/nvidia/nvidia-oot/include/media/gmsl-link.h:29:define GMSL_CSI_PORT_A 0x0
AGX/Linux_for_Tegra/rootfs/usr/src/nvidia/nvidia-oot/include/media/gmsl-link.h:30:define GMSL_CSI_PORT_B 0x1
AGX/Linux_for_Tegra/rootfs/usr/src/nvidia/nvidia-oot/include/media/gmsl-link.h:31:define GMSL_CSI_PORT_C 0x2
AGX/Linux_for_Tegra/rootfs/usr/src/nvidia/nvidia-oot/include/media/gmsl-link.h:32:define GMSL_CSI_PORT_D 0x3
AGX/Linux_for_Tegra/rootfs/usr/src/nvidia/nvidia-oot/include/media/gmsl-link.h:33:define GMSL_CSI_PORT_E 0x4
AGX/Linux_for_Tegra/rootfs/usr/src/nvidia/nvidia-oot/include/media/gmsl-link.h:34:define GMSL_CSI_PORT_F 0x5
Thank you in advance for your prompt response!
Best regard.
Thank you.

3

Both of them are incorrect.

The brick 2(EF) and 3(FH) only support one camera for 1x/2x/4x lanes configuration. However, the PORT # is correct in the right side.

4

I would like to connect camera below diagram

image
image1460×1590 170 KB

It means deserializer A uses Brick 0 and Brick 1 and deserializer B uses Brick 2 and Brick 3.
Is it possible with AGX Orin?
I always thank you Shane for your prompt and kind response !!!
Thank you.
Best regard.

5

This case should be fine for NVCSI/VI.

Thanks

6

Hello Shane
Thank you so much for your prompt response!
My system’s configuration is below.

image
image1715×1125 194 KB

Could you please review my dts configuration whether valid or not?
I attached my dts for above diagram.
tegra234-p3737-camera-imx390-overlay.dts.txt (49.2 KB)
I have been succss to port many cameras for your kind help.
Thank you.
Best regard.

7

Looks like no error for the port-index/bus-width.

Thanks

8

Hello Shane
I always thank you for your kind and prompt response!!!
I have to change my system as below.

image
image2404×1056 328 KB

Could you tell me tegra_sinterface_? of the diagram.https://global.discourse-cdn.com/nvidia/original/4X/e/2/6/e26462f5e4d2af129bb81c2f3a90898604319206.png
Could you confirm whether GMSL_CIS_PORT# is equal to PORT NUMBER of the diagram.
Could you tell me below picture’s dst-csi-port for orange colored tegra_sinterface
I know values for tegra_sinterface_a,tegra_sinterface_b,tegra_sinterface_c and ,tegra_sinterface_d
gmsl-link {
src-csi-port = “a”;
dst-csi-port = “e ?, or f?”;
serdes-csi-link = “b”;
csi-mode = “1x4”;
st-vc = <0>;
vc-id = <0>;
num-lanes = <4>;
streams = “raw8”;
};

Thank you in advance for your prompt response!!

9

This could be the GMSL driver setting. Please check the driver for the detail. Suppose doesn’t matter with tegra_sinterface.

10

Hello Shane
Thank you so much for your prompt respose!!!
Could you tell me for tegra_sinterface values for orange colored box?
mode0 {/mode IMX390_MODE_1920X1200_CROP_30FPS/
mclk_khz = “24000”;
num_lanes = “2”;
tegra_sinterface = “serial_e”;
vc_id = “2”;
phy_mode = “DPHY”;
discontinuous_clk = “no”;
dpcm_enable = “false”;

Could you tell me GMSL related dst-csi-port.
I set dst-cis-port like below
dst-csi-port-a = GMSL_CSI_PORT_A
dst-csi-port-b = GMSL_CSI_PORT_B
dst-csi-port-c = GMSL_CSI_PORT_C
dst-csi-port-d = GMSL_CSI_PORT_D
It was successful.
I would linke to know tegra_sinterface and dst-csi-port for orange colored box items.

Thank you in advance for your prompt response!!!

11

I don’t have idea for the dst-csi-port-* but the tegra_sinterface is like mapping like below.

port-index tegra_sinterface
0 a
1 b
2 c
3 d
4 e

12

Thank you so much!!!
Your reponse is really so prompt !!
port-index tegra_sinterface
0 a
1 b
2 c
3 d
4 e
5 f
for port-index 5 → tegra_sinterface must be f, am I right?

13

Usually EF/GH bricks only support one stream for 1x/2x/4x
And usually start from CSI-E.

CSI VI tegra_sinterface
0 0 a
1 1 b
2 2 c
3 3 d
4/5 4 e/f
6/7 5 g/h

14

Shane, thank you so much for your kind and prompt response. I will test it soon and update the issue.

16

Is this still an issue to support? Any result can be shared?

18

Hello kayccc
Sorry for late update.
Could you please close this issue.
Although It’s not finished,I am doing other things for a while.
Thank you for support.
Best regard.

20

OK, thanks for your update.