Auto power on sequence

nVIDIA stuff

Please present the automatic power on sequence of Jetson TX1 in the timing chart.
Please add in the form added to Figure 4 in Section 3.4 of the “OEM Product Design Guide”.
Add the CHARGER_PRSNT # signal.
With words alone, the definition is ambiguous.

Best Regards.

Auto-Power-On support is optional, it should not be added to standard power up sequence timing. Also the design request for CHARGER_PRSNT# pin is simple and clear – a minimum delay of 300ms from the point VDD_IN reaches its minimum level (5.5V) before it can be driven low and should be held low for > 200us.

Hi Trumany

Thanks for the reply.

Whether or not the Auto Power-On mode is optional is not important.
The problem is that there is no timing chart (diagram) entitled “Auto Power-On Sequence”. It is necessary to describe the signal related to Power management in the timing chart.
We need to use Auto Power-On mode.
Therefore, nVIDIA needs to be clearly defined.

best regards.

Hi Blue, as you can see in chapter 3.8, there are three kinds of ways to implement auto power on function, even NV gave the examples, customers still could choose other devices. Showing the detail timing of all possible devices is impossible and unnecessary, so we give the least requests as previously said. I do think the words of that is clear to customers. If you don’t think so, can you please tell which part make you confused?

Our confusion is that there is no provision as a Jetson module.
Since it can be understood that it can not support for each option circuit and device, please clarify the regulation as a module.
For that, we need a diagram equivalent to the Power-On sequence.
Please also present time regulations.

“a minimum delay of 300ms from the point VDD_IN reaches its minimum level (5.5V) before it can be driven low and should be held low for > 200us.”, this is the request for CHARGER_PRSNT#, after that the module power sequence is same as the latter of POWER_BTN# in Figure 4. In fact, you can take the auto power on as a controlled action of ONKEY pressing.

If you replace the POWER_BTN # signal in “Figure 4: Power up sequense” with CHARGER_PRSNT #, the CHARGER_PRSNT # signal will continue to assert ‘L’ until the dashed line 4 and Jetson_TX 1 System Power will turn on when ‘H’ A sequence after the broken line 5 is required.
That is, the rising edge of the POWER_BTN # signal and the rising edge of the CHARGER_PRSNT # signal have the same meaning.
Is this understanding

It is additional confirmation.
The time specification until dashed line 4 that negates the CHARGER_PRSNT # signal with ‘H’ after negating the VIN_PWR_BAD # signal with broken line 2 is> 200 [us].
Is it that?

POWER_BTN# and CHARGER_PRSNT# are both low level enable, not edge enable, they have their own debounced time. The ‘300ms’ contains the duration request from stable VDD_IN to high VIN_PWR_BAD#, so to power on system, only need to implement >200 us low on CHARGER_PRSNT# after the ‘300ms’.

Again, I would like a timing chart equivalent to Figure 4.
That is clear.