Can Orin NX module boot from nvme on pcie2？

243953617 · February 22, 2023, 7:33am

We designed a carrier board to be compatible with multiple core boards。
For some reason, the ssd interface of Orin NX can only be connected from pcie2. How do I configure and write the system?
I used an Orin NX module + Xavier NX devkit carrier board to flash successfully。
by cmd：sudo ./tools/kernel_flash/l4t_initrd_flash.sh --external-device nvme0n1p1 -c tools/kernel_flash/flash_l4t_external.xml -p “-c bootloader/t186ref/cfg/flash_t234_qspi.xml” --showlogs --network usb0 p3509-a02+p3767-0000 internal

After we replace it on our base plate，they make error on step 3：

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Step 3: Start the flashing process *
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Waiting for target to boot-up…
Waiting for target to boot-up…
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Waiting for target to boot-up…
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Waiting for target to boot-up…
Waiting for target to boot-up…
Waiting for target to boot-up…
Waiting for target to boot-up…
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Waiting for target to boot-up…
Waiting for target to boot-up…
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Waiting for target to boot-up…
Waiting for target to boot-up…
Waiting for target to boot-up…
Waiting for device to expose ssh …RTNETLINK answers: File exists
RTNETLINK answers: File exists
Waiting for device to expose ssh …Run command: flash on fc00:1:1:0::2
SSH ready
blockdev: cannot open /dev/mmcblk0boot0: No such file or directory
[ 0]: l4t_flash_from_kernel: Starting to create gpt for emmc
Active index file is /mnt/internal/flash.idx
Number of lines is 58
max_index=57
[ 10]: l4t_flash_from_kernel: Successfully create gpt for emmc
[ 10]: l4t_flash_from_kernel: Starting to create gpt for external device
Active index file is /mnt/external/flash.idx
Number of lines is 17
max_index=16
writing item=1, 9:0:primary_gpt, 512, 19968, gpt_primary_9_0.bin, 16896, fixed--0, 0ef91466f0476b4719fa4d889d01abf3f3abe980
Error: Could not stat device /dev/nvme0n1 - No such file or directory.
Flash failure
Cleaning up…
exportfs: /etc/exports [1]: Neither ‘subtree_check’ or ‘no_subtree_check’ specified for export “*:/home/lyi/Work/imx/imx7/NFS”.
Assuming default behaviour (‘no_subtree_check’).
NOTE: this default has changed since nfs-utils version 1.0.x

exportfs: /etc/exports [2]: Neither ‘subtree_check’ or ‘no_subtree_check’ specified for export “*:/home/lyi/Work/imx/imx6/NFS”.
Assuming default behaviour (‘no_subtree_check’).
NOTE: this default has changed since nfs-utils version 1.0.x

exportfs: /etc/exports [3]: Neither ‘subtree_check’ or ‘no_subtree_check’ specified for export “*:/home/lyi/Work/”.
Assuming default behaviour (‘no_subtree_check’).
NOTE: this default has changed since nfs-utils version 1.0.x

Q2：I need to recompile the whole project every time I flash the system. How can I skip the previous step of system building?
Just like we did with the -r argument（./flash.sh -r jetson-xavier-nx-devkit-emmc mmcblk0p1）

thanks！

243953617 · February 22, 2023, 7:39am

All the log data：
log.txt (256.9 KB)

WayneWWW · February 22, 2023, 9:25am

Hi,

Please boot from usb first and see if your pcie could detect this nvme or not.
Make it more easier to understand, “initrd flash” depends on the device tree. Thus, you need to make sure device tree is okay to run your pcie device. Otherwise it won’t detect and won’t be able to flash.

Also, which pin is pcie2?

243953617 · February 22, 2023, 9:32am

Thanks. I’ll try it。
And how do I burn the system fast?I had to wait long time for ”Making system.img“ 。

243953617 · February 24, 2023, 9:48am

hi，
I successfully booted the system using usb，and i find pcie could not detect this nvme。

the pcie port is pcie2 ：

the pin num ：

dmesg about pcie：
sudo dmesg | grep “pcie”
[ 6.034576] tegra194-pcie 14100000.pcie: Adding to iommu group 8
[ 6.047263] tegra194-pcie 14100000.pcie: Using GICv2m MSI allocator
[ 6.054469] tegra194-pcie 14160000.pcie: Adding to iommu group 9
[ 6.066628] tegra194-pcie 14160000.pcie: Using GICv2m MSI allocator
[ 6.073536] tegra194-pcie 140a0000.pcie: Adding to iommu group 10
[ 6.085801] tegra194-pcie 140a0000.pcie: Using GICv2m MSI allocator
[ 6.092930] tegra194-pcie 140a0000.pcie: Failed to get slot regulators: -517
[ 8.346047] tegra194-pcie 14100000.pcie: Using GICv2m MSI allocator
[ 8.353602] tegra194-pcie 14100000.pcie: host bridge /pcie@14100000 ranges:
[ 8.364600] tegra194-pcie 14100000.pcie: IO 0x0030100000…0x00301fffff → 0x0030100000
[ 8.373285] tegra194-pcie 14100000.pcie: MEM 0x20a8000000…0x20afffffff → 0x0040000000
[ 8.389568] tegra194-pcie 14100000.pcie: MEM 0x2080000000…0x20a7ffffff → 0x2080000000
[ 9.499238] tegra194-pcie 14100000.pcie: Phy link never came up
[ 9.505400] tegra194-pcie 14100000.pcie: PCI host bridge to bus 0001:00
[ 9.579812] pcieport 0001:00:00.0: Adding to iommu group 8
[ 9.585665] pcieport 0001:00:00.0: PME: Signaling with IRQ 54
[ 9.591983] pcieport 0001:00:00.0: AER: enabled with IRQ 54
[ 9.617410] tegra194-pcie 14160000.pcie: Using GICv2m MSI allocator
[ 9.625053] tegra194-pcie 14160000.pcie: host bridge /pcie@14160000 ranges:
[ 9.632223] tegra194-pcie 14160000.pcie: IO 0x0036100000…0x00361fffff → 0x0036100000
[ 9.640903] tegra194-pcie 14160000.pcie: MEM 0x2428000000…0x242fffffff → 0x0040000000
[ 9.649578] tegra194-pcie 14160000.pcie: MEM 0x2140000000…0x2427ffffff → 0x2140000000
[ 10.767304] tegra194-pcie 14160000.pcie: Phy link never came up
[ 10.773445] tegra194-pcie 14160000.pcie: PCI host bridge to bus 0004:00
[ 10.847941] pcieport 0004:00:00.0: Adding to iommu group 9
[ 10.853783] pcieport 0004:00:00.0: PME: Signaling with IRQ 56
[ 10.859948] pcieport 0004:00:00.0: AER: enabled with IRQ 56
[ 10.885286] tegra194-pcie 140a0000.pcie: Using GICv2m MSI allocator
[ 10.891835] tegra194-pcie 140a0000.pcie: Failed to get slot regulators: -517
[ 10.938359] tegra194-pcie 140a0000.pcie: Using GICv2m MSI allocator
[ 11.067415] tegra194-pcie 140a0000.pcie: host bridge /pcie@140a0000 ranges:
[ 11.074594] tegra194-pcie 140a0000.pcie: IO 0x002a100000…0x002a1fffff → 0x002a100000
[ 11.083285] tegra194-pcie 140a0000.pcie: MEM 0x3528000000…0x352fffffff → 0x0040000000
[ 11.091963] tegra194-pcie 140a0000.pcie: MEM 0x3240000000…0x3527ffffff → 0x3240000000
[ 11.205824] tegra194-pcie 140a0000.pcie: Link up
[ 11.213818] tegra194-pcie 140a0000.pcie: PCI host bridge to bus 0008:00
[ 11.417249] pcieport 0008:00:00.0: Adding to iommu group 10
[ 11.423195] pcieport 0008:00:00.0: PME: Signaling with IRQ 58
[ 11.429185] pcieport 0008:00:00.0: AER: enabled with IRQ 58

all dmesg log：
dmesg.log (64.6 KB)

I have the following questions.

Is port pcie2 started?
is boot enabled from other pcie ports？
What configurations and parameters do I need to modify to enable ssd booting from pcie2?

That’s been bothering me for a long time. Thank you.

243953617 · February 27, 2023, 6:42am

hi.
Do I need to modify the pin configuration and device tree?
I downloaded the <<Jetson_Orin_NX_series_and_Orin_Nano_series_Pinmux_Config_Template.xlsm>>,The default pin is pcie2,Does that mean I don’t have to change it?

thanks.

kayccc · March 15, 2023, 2:49am

Sorry for the late response, have you managed to get issue resolved or still need the support? Thanks

cfall · March 29, 2023, 3:01pm

Hi, not sure why this is marked as resolved. Have you managed to find a solution to your problem? Can someone help in providing some answers?

WayneWWW · March 29, 2023, 3:12pm

please refer to the adaptation guide document in the l4t devleoper guide for the PCIe part software porting.

You need to check the version >= rel-35.2.1 because this is where Orin NX starts to support.

If you cannot find the document, search “l4t archive” and the first page will lead you there.

cfall · March 31, 2023, 5:25am

Thanks @WayneWWW.

system · April 14, 2023, 5:26am

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