Can't get spi0 pinmux to take effect

Hey,

I’ve tried to enable spi0 in the driver and then create a pinmux phandle generated from the excel spreadsheet but it doesn’t acctualy link the pins to the driver.

kernel_tegra234-p3767-0003-super-p3768-0000-a0 - Copy.txt (433.6 KB)

kernel_tegra234-p3767-0003-super-p3768-0000-a0-excel.txt (433.5 KB)

I’ve uploaded my dtb from the jetson orin that I modified, as well as the one that is generated from the excel sheet. I’ve combined the spi0 pins into two groups as such: “spi1_pins_pz: spi1_pins_pz {
nvidia,pins = “spi1_sck_pz3”,
“spi1_miso_pz4”,
“spi1_mosi_pz5”;
nvidia,function = “spi1”;

		/* common settings for SCK/MISO/MOSI */
		nvidia,pull = <0x01>;          // pull-up (or 0x00 = none if you prefer)
		nvidia,tristate = <0x00>;      // drive enabled
		nvidia,enable-input = <0x01>;  // needed for MISO, harmless for others
		nvidia,io-high-voltage = <0x00>;
		nvidia,lpdr = <0x00>;
	 };

	spi1_cs0_pz: spi1_cs0_pz {
		nvidia,pins = "spi1_cs0_pz6";
		nvidia,function = "spi1";

		/* special settings for chip-select */
		nvidia,pull = <0x02>;          // whatever you were using for CS
		nvidia,tristate = <0x00>;
		nvidia,enable-input = <0x00>;  // usually output-only
		nvidia,io-high-voltage = <0x00>;
		nvidia,lpdr = <0x00>;
	};

“. I referenced them to the spi0 driver which is acctualy labeled spi1 in the driver as follows: “ spi@3210000 {

    compatible = "nvidia,tegra186-spi";

    reg = <0x00 0x3210000 0x00 0x10000>;

    interrupts = <0x00 0x24 0x04>;

    #address-cells = <0x01>;

    #size-cells = <0x00>;

    iommus = <0x06 0x04>;

    dma-coherent;

    dmas = <0x3f 0x0f 0x3f 0x0f>;

    dma-names = "rx\\0tx";

    spi-max-frequency = <0x3dfd240>;

    nvidia,clk-parents = "pll_p\\0clk_m";

    clocks = <0x02 0x87 0x02 0x66 0x02 0x0e>;

    clock-names = "spi\\0pll_p\\0clk_m";

    resets = <0x02 0x5b>;

    reset-names = "spi";

    status = "okay";

    phandle = <0x312>;

    pinctrl-names = "default";

    pinctrl-0 = <&spi1_pins_pz &spi1_cs0_pz>;



    prod-settings {

        #prod-cells = <0x04>;



        prod {

            prod = <0x00 0x194 0x80000000 0x00>;

        };

    };



    spi@0 {

        compatible = "tegra-spidev";

        reg = <0x00>;

        spi-max-frequency = <0x2faf080>;

        status = "okay";



        controller-data {

            nvidia,enable-hw-based-cs;

            nvidia,rx-clk-tap-delay = <0x10>;

            nvidia,tx-clk-tap-delay = <0x00>;

        };

    };



    spi@1 {

        compatible = "tegra-spidev";

        reg = <0x01>;

        spi-max-frequency = <0x2faf080>;



        controller-data {

            nvidia,enable-hw-based-cs;

            nvidia,rx-clk-tap-delay = <0x10>;

            nvidia,tx-clk-tap-delay = <0x00>;

        };

    };

};” using pinctrl-0.

It’s not assigning it confirmed usign this command: “g_nano@ubuntu:/proc/device-tree$ hexdump -C spi@3210000/pinctrl-0
00000000 00 00 04 9c 00 00 04 9d |…|
00000008”.

Please help…

*** Please note that this reply is generated by LLM automatically ***

Based on the provided context, it appears that you are trying to enable SPI0 on the Jetson Orin Nano and create a pinmux phandle generated from the Excel spreadsheet. However, the pins are not being linked to the driver.

Firstly, let’s clarify the pinmux configuration for SPI0 on the Jetson Orin Nano. According to the Jetson Orin NX Series and Jetson Orin Nano Series Product Design Guide (DG-10931-001_v1.4), the SPI0 pins are:

  • SPI0_SCK (GP47_SPI1_SCK)
  • SPI0_MISO (GP48_SPI1_MISO)
  • SPI0_MOSI (GP49_SPI1_MOSI)
  • SPI0_CS0* (GP50_SPI1_CS0)
  • SPI0_CS1* (GP51_SPI1_CS1)

These pins are located on the Orin module and are brought out to the carrier board.

In your case, you have combined the SPI0 pins into two groups: spi1pinspz and spi1pinspz. You have also referenced them to the SPI0 driver, which is labeled as spi1 in the driver.

However, the issue seems to be that the pins are not being assigned to the driver. You have confirmed this using the command gnanoubuntu proc device-tree hexdump C spi3210000.pinctrl-0, which shows that the pinmux configuration is not being applied.

To resolve this issue, you need to ensure that the pinmux configuration is correct and that the pins are being assigned to the driver. Here are a few things you can check:

  1. Verify that the pinmux configuration in your device tree is correct. Make sure that the spi1pinspz and spi1pinspz groups are defined correctly and that they are referenced to the spi1 driver.
  2. Check that the nvidia,pins property is set correctly in the device tree. This property should specify the pin numbers and functions for the SPI0 pins.
  3. Ensure that the nvidia,function property is set correctly in the device tree. This property should specify the function of the SPI0 pins (in this case, spi1).
  4. Verify that the pinmux configuration is being applied correctly. You can do this by checking the output of the gnanoubuntu proc device-tree hexdump C spi3210000.pinctrl-0 command.

If you are still having issues, you may want to try using the jetson-orin-nano-devkit configuration file, which is provided in the Jetson Orin Nano Developer Kit documentation. This file should have the correct pinmux configuration for the SPI0 pins.

Additionally, you can try using the l4t_initrd_flash.sh script to flash the device tree and pinmux configuration to the Jetson Orin Nano. This script is provided in the Jetson Orin Nano Developer Kit documentation and can be used to flash the device tree and pinmux configuration to the device.

I hope this helps! Let me know if you have any further questions or if there’s anything else I can help with.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

  1. I already did that which is clearly indicarted in the file I provided you. Do not ask for things I’ve already provided.
    2. What should I look for? I gave you the DT and I did it according to what I thought was right.
    3. What is the setting for nvidia,function? Again I took what was provided from the default DT form nvidia and things aren’t working. I would just be looking at the same thing I already have with nothing to compare it to. Pretty useless advice.
    4. I litteraly gave you that information, what is going on here?

    Yes I’m still having issues lol, can you acctualy help? Is there management I can escalate this too because I paid money for these devices and I need support. The documentation is not clear on how to do this stuff nor does it provide a clear reference to what the pin names should be.

    Ummm… you get a thumbs down? You didn’t do anything. What is going on here?!

Hi SterlingArcher,

Are you using the devkit or custom board for Orin Nano?
What’s the Jetpack version in use?

Please share the result of the following commands on your board.

// SPI1_SCK
$ sudo busybox devmem 0x0243d028
// SPI1_MISO
$ sudo busybox devmem 0x0243d018
// SPI1_MOSI
$ sudo busybox devmem 0x0243d040
// SPI1_CS0
$ sudo busybox devmem 0x0243d008
// SPI1_CS1
$ sudo busybox devmem 0x0243d038

Hey,

It is a custom board running: “R35 (release), REVISION: 6.1, GCID: 39721438, BOARD: t186ref, EABI: aarch64, DATE: Tue Mar 4 10:13:09 UTC 2025” and I’ve disabled the search for eeprom so that my system will boot on our prototype board.

Here is the output you requested:

root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# sudo busybox devmem 0x0243d028
0x00001055
root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# sudo busybox devmem 0x0243d018
0x00000055
root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# sudo busybox devmem 0x0243d040
0x00000055
root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# sudo busybox devmem 0x0243d008
0x00000059
root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# sudo busybox devmem 0x0243d038
0x00000059

from_live - Copy.txt (428.0 KB) This text file is the live device tree running in the system and I can see spi1 driver node and corresponding pinmux group is added as I intended however, the pinmux isn’t assigned:

root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# cat /sys/kernel/debug/pinctrl/*/pinmux-pins
Pinmux settings per pin
Format: pin (name): mux_owner gpio_owner hog?
pin 0 (DAP6_SCLK_PA0): (MUX UNCLAIMED) tegra234-gpio:348
pin 1 (DAP6_DOUT_PA1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 2 (DAP6_DIN_PA2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 3 (DAP6_FS_PA3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 4 (DAP4_SCLK_PA4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 5 (DAP4_DOUT_PA5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 6 (DAP4_DIN_PA6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 7 (DAP4_FS_PA7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 8 (SOC_GPIO08_PB0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 9 (QSPI0_SCK_PC0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 10 (QSPI0_CS_N_PC1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 11 (QSPI0_IO0_PC2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 12 (QSPI0_IO1_PC3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 13 (QSPI0_IO2_PC4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 14 (QSPI0_IO3_PC5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 15 (QSPI1_SCK_PC6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 16 (QSPI1_CS_N_PC7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 17 (QSPI1_IO0_PD0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 18 (QSPI1_IO1_PD1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 19 (QSPI1_IO2_PD2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 20 (QSPI1_IO3_PD3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 21 (EQOS_TXC_PE0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 22 (EQOS_TD0_PE1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 23 (EQOS_TD1_PE2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 24 (EQOS_TD2_PE3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 25 (EQOS_TD3_PE4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 26 (EQOS_TX_CTL_PE5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 27 (EQOS_RD0_PE6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 28 (EQOS_RD1_PE7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 29 (EQOS_RD2_PF0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 30 (EQOS_RD3_PF1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 31 (EQOS_RX_CTL_PF2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 32 (EQOS_RXC_PF3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 33 (EQOS_SMA_MDIO_PF4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 34 (EQOS_SMA_MDC_PF5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 35 (SOC_GPIO13_PG0): (MUX UNCLAIMED) tegra234-gpio:383
pin 36 (SOC_GPIO14_PG1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 37 (SOC_GPIO15_PG2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 38 (SOC_GPIO16_PG3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 39 (SOC_GPIO17_PG4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 40 (SOC_GPIO18_PG5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 41 (SOC_GPIO19_PG6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 42 (SOC_GPIO20_PG7): (MUX UNCLAIMED) tegra234-gpio:390
pin 43 (SOC_GPIO21_PH0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 44 (SOC_GPIO22_PH1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 45 (SOC_GPIO06_PH2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 46 (UART4_TX_PH3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 47 (UART4_RX_PH4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 48 (UART4_RTS_PH5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 49 (UART4_CTS_PH6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 50 (SOC_GPIO41_PH7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 51 (SOC_GPIO42_PI0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 52 (SOC_GPIO43_PI1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 53 (SOC_GPIO44_PI2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 54 (GEN1_I2C_SCL_PI3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 55 (GEN1_I2C_SDA_PI4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 56 (CPU_PWR_REQ_PI5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 57 (SOC_GPIO07_PI6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 58 (SDMMC1_CLK_PJ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 59 (SDMMC1_CMD_PJ1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 60 (SDMMC1_DAT0_PJ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 61 (SDMMC1_DAT1_PJ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 62 (SDMMC1_DAT2_PJ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 63 (SDMMC1_DAT3_PJ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 64 (PEX_L0_CLKREQ_N_PK0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 65 (PEX_L0_RST_N_PK1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 66 (PEX_L1_CLKREQ_N_PK2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 67 (PEX_L1_RST_N_PK3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 68 (PEX_L2_CLKREQ_N_PK4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 69 (PEX_L2_RST_N_PK5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 70 (PEX_L3_CLKREQ_N_PK6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 71 (PEX_L3_RST_N_PK7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 72 (PEX_L4_CLKREQ_N_PL0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 73 (PEX_L4_RST_N_PL1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 74 (PEX_WAKE_N_PL2): (MUX UNCLAIMED) tegra234-gpio:422
pin 75 (SOC_GPIO34_PL3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 76 (DP_AUX_CH0_HPD_PM0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 77 (DP_AUX_CH1_HPD_PM1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 78 (DP_AUX_CH2_HPD_PM2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 79 (DP_AUX_CH3_HPD_PM3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 80 (SOC_GPIO55_PM4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 81 (SOC_GPIO36_PM5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 82 (SOC_GPIO53_PM6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 83 (SOC_GPIO38_PM7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 84 (DP_AUX_CH3_N_PN0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 85 (SOC_GPIO39_PN1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 86 (SOC_GPIO40_PN2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 87 (DP_AUX_CH1_P_PN3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 88 (DP_AUX_CH1_N_PN4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 89 (DP_AUX_CH2_P_PN5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 90 (DP_AUX_CH2_N_PN6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 91 (DP_AUX_CH3_P_PN7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 92 (EXTPERIPH1_CLK_PP0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 93 (EXTPERIPH2_CLK_PP1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 94 (CAM_I2C_SCL_PP2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 95 (CAM_I2C_SDA_PP3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 96 (SOC_GPIO23_PP4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 97 (SOC_GPIO24_PP5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 98 (SOC_GPIO25_PP6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 99 (PWR_I2C_SCL_PP7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 100 (PWR_I2C_SDA_PQ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 101 (SOC_GPIO28_PQ1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 102 (SOC_GPIO29_PQ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 103 (SOC_GPIO30_PQ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 104 (SOC_GPIO31_PQ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 105 (SOC_GPIO32_PQ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 106 (SOC_GPIO33_PQ6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 107 (SOC_GPIO35_PQ7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 108 (SOC_GPIO37_PR0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 109 (SOC_GPIO56_PR1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 110 (UART1_TX_PR2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 111 (UART1_RX_PR3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 112 (UART1_RTS_PR4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 113 (UART1_CTS_PR5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 114 (GPU_PWR_REQ_PX0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 115 (CV_PWR_REQ_PX1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 116 (GP_PWM2_PX2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 117 (GP_PWM3_PX3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 118 (UART2_TX_PX4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 119 (UART2_RX_PX5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 120 (UART2_RTS_PX6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 121 (UART2_CTS_PX7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 122 (SPI3_SCK_PY0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 123 (SPI3_MISO_PY1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 124 (SPI3_MOSI_PY2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 125 (SPI3_CS0_PY3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 126 (SPI3_CS1_PY4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 127 (UART5_TX_PY5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 128 (UART5_RX_PY6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 129 (UART5_RTS_PY7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 130 (UART5_CTS_PZ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 131 (USB_VBUS_EN0_PZ1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 132 (USB_VBUS_EN1_PZ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 133 (SPI1_SCK_PZ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 134 (SPI1_MISO_PZ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 135 (SPI1_MOSI_PZ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 136 (SPI1_CS0_PZ6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 137 (SPI1_CS1_PZ7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 138 (CAN0_DOUT_PAA0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 139 (CAN0_DIN_PAA1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 140 (CAN1_DOUT_PAA2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 141 (CAN1_DIN_PAA3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 142 (CAN0_STB_PAA4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 143 (CAN0_EN_PAA5): (MUX UNCLAIMED) tegra234-gpio-aon:321
pin 144 (SOC_GPIO49_PAA6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 145 (CAN0_ERR_PAA7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 146 (SPI5_SCK_PAC0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 147 (SPI5_MISO_PAC1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 148 (SPI5_MOSI_PAC2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 149 (SPI5_CS0_PAC3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 150 (SOC_GPIO57_PAC4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 151 (SOC_GPIO58_PAC5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 152 (SOC_GPIO59_PAC6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 153 (SOC_GPIO60_PAC7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 154 (SOC_GPIO45_PAD0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 155 (SOC_GPIO46_PAD1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 156 (SOC_GPIO47_PAD2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 157 (SOC_GPIO48_PAD3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 158 (UFS0_REF_CLK_PAE0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 159 (UFS0_RST_N_PAE1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 160 (PEX_L5_CLKREQ_N_PAF0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 161 (PEX_L5_RST_N_PAF1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 162 (PEX_L6_CLKREQ_N_PAF2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 163 (PEX_L6_RST_N_PAF3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 164 (PEX_L7_CLKREQ_N_PAG0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 165 (PEX_L7_RST_N_PAG1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 166 (PEX_L8_CLKREQ_N_PAG2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 167 (PEX_L8_RST_N_PAG3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 168 (PEX_L9_CLKREQ_N_PAG4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 169 (PEX_L9_RST_N_PAG5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 170 (PEX_L10_CLKREQ_N_PAG6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 171 (PEX_L10_RST_N_PAG7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 172 (CAN1_STB_PBB0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 173 (CAN1_EN_PBB1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 174 (SOC_GPIO50_PBB2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 175 (CAN1_ERR_PBB3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 176 (SPI2_SCK_PCC0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 177 (SPI2_MISO_PCC1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 178 (SPI2_MOSI_PCC2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 179 (SPI2_CS0_PCC3): (MUX UNCLAIMED) tegra234-gpio-aon:331
pin 180 (TOUCH_CLK_PCC4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 181 (UART3_TX_PCC5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 182 (UART3_RX_PCC6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 183 (GEN2_I2C_SCL_PCC7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 184 (GEN2_I2C_SDA_PDD0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 185 (GEN8_I2C_SCL_PDD1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 186 (GEN8_I2C_SDA_PDD2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 187 (SCE_ERROR_PEE0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 188 (VCOMP_ALERT_PEE1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 189 (AO_RETENTION_N_PEE2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 190 (BATT_OC_PEE3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 191 (POWER_ON_PEE4): (MUX UNCLAIMED) tegra234-gpio-aon:343
pin 192 (SOC_GPIO26_PEE5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 193 (SOC_GPIO27_PEE6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 194 (BOOTV_CTL_N_PEE7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 195 (HDMI_CEC_PGG0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 196 (EQOS_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 197 (QSPI_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 198 (SDMMC1_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)

I also get this from dmsg:

root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# dmesg | grep -i tegra186-spi

root@ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# dmesg | grep -i “3210000.spi”

[ 16.695796] spi-tegra114 3210000.spi: there is not valid maps for state default [ 16.695810] spi-tegra114 3210000.spi: there is not valid maps for state default [ 16.695945] spi-tegra114 3210000.spi: Adding to iommu group 2

They are not the expected results to me as the SFIO bit (bit 10) is not enabled for SPI usage.

As you are using the custom carrier board, I would suggest you using pinmux spreadsheet configure SPI related pins and generate pinmux/gpio dtsi and refer to Jetson Orin NX and Nano Series — Generating the Pinmux dtsi Files to apply the change.

Please not that pinmux/gpio dtsi are loaded in early boot state(i.e. MB1) rather than kernel.

Hey so I followed the tutorial you gave me and if I decompile the live dts running on the system it still doesn’t add the pinmux for spi@3210000.

I used the spreadsheet to generate orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi, orin-jetson-orin-nano-nx-pinmux-dp-gpio-default.dtsi, and orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default.dtsi. I put pad voltages and pinmux to JetPack_5.1.5_L…NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/ and gpio file to JetPack_5.1.5_L…NANO_TARGETS/Linux_for_Tegra/bootloader/. I then edited p3767.conf.common under #BCT args:” and added PINMUX_CONFIG=”orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi” and PMC_CONFIG=”orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default.dtsi”. I commented out GPIOINT_CONFIG that was there and added GPIOINT_CONFIG=”orin-jetson-orin-nano-nx-pinmux-dp-gpio-default.dtsi”. I saved and then executed sudo ./flash.sh jetson-orin-nano-devkit internal and flashed the SoM. I then booted it on the devkit and extracted the running dtb and I still don’t see my changes applied.

I also added an echo in p3767.conf.common so that I know it’s using the correct one during flashing and it is.

I’m not sure what I’m doing wrong.

live.txt (427.9 KB)

root@tegra-ubuntu:/sys/kernel/debug/pinctrl# busybox devmem 0x0243d028
0x00001055
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d018
0x00000055
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d040
0x00000055
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d008
0x00000059
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d038
0x00000059

It looks like the flashing process is still using some default dtsi files rather than what I chose in p3767.conf.common. This is part of the terminal output during flashing:

/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/L4TConfiguration_updated.dts: Warning (unit_address_vs_reg): Node /fragment@0 has a unit name, but no reg property
/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/L4TConfiguration.dtbo: Warning (unit_address_vs_reg): Node /fragment@0 has a unit name, but no reg property
./tegraflash.py --bl uefi_jetson_with_dtb.bin --odmdata gbe-uphy-config-8,hsstp-lane-map-3,hsio-uphy-config-0 --overlay_dtb L4TConfiguration.dtbo,tegra234-p3767-overlay.dtbo,tegra234-p3768-overlay.dtbo, --bldtb tegra234-p3767-0003-p3768-0000-a0.dtb --applet mb1_t234_prod.bin --cmd “flash; reboot” --cfg flash.xml --chip 0x23 --concat_cpubl_bldtb --cpubl uefi_jetson.bin --minratchet_config tegra234-mb1-bct-ratchet-p3767-0000.dts --device_config tegra234-mb1-bct-device-p3767-0000.dts --misc_config tegra234-mb1-bct-misc-p3767-0000.dts --pinmux_config tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi --pmic_config tegra234-mb1-bct-pmic-p3767-0000-a02.dts --pmc_config tegra234-mb1-bct-padvoltage-p3767-dp-a03.dtsi --deviceprod_config tegra234-mb1-bct-cprod-p3767-0000.dts --prod_config tegra234-mb1-bct-prod-p3767-0000.dts --scr_config tegra234-mb2-bct-scr-p3767-0000.dts --wb0sdram_config tegra234-p3767-0001-wb0sdram-l4t.dts --br_cmd_config tegra234-mb1-bct-reset-p3767-0000.dts --uphy tegra234-mb1-bct-uphylane-si.dtsi --dev_params tegra234-br-bct-p3767-0000-l4t.dts,tegra234-br-bct_b-p3767-0000-l4t.dts --mb2bct_cfg tegra234-mb2-bct-misc-p3767-0000.dts --bins “psc_fw pscfw_t234_prod.bin; mts_mce mce_flash_o10_cr_prod.bin; mb2_applet applet_t234.bin; mb2_bootloader mb2_t234.bin; xusb_fw xusb_t234_prod.bin; dce_fw display-t234-dce.bin; nvdec nvdec_t234_prod.fw; bpmp_fw bpmp_t234-TE950M-A1_prod.bin; bpmp_fw_dtb tegra234-bpmp-3767-0003-3509-a02.dtb; sce_fw camera-rtcpu-sce.img; rce_fw camera-rtcpu-t234-rce.img; ape_fw adsp-fw.bin; spe_fw spe_t234.bin; tos tos-optee_t234.img; eks eks_t234.img” --sdram_config tegra234-p3767-0001-sdram-l4t.dts --cust_info custinfo_out.bin --ramcode 2 --bct_backup --boot_chain A

For example --pmc_config is using a default instead of orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default.dtsi.

You don’t need to do this as orin-jetson-orin-nano-nx-pinmux-dp-gpio-default.dtsi has been included by orin-jetson-orin-nano-nx-pinmux-dp-gpio-default.dtsi. GPIOINT_CONFIG is used for GPIO interrupt configuration.

Please update jetson-orin-nano-devkit.conf instead of p3767.conf.common as the p3767.conf.common is included by jetson-orin-nano-devkit.conf and the PINMUX_CONFIG and PMC_CONFIG will be overwritten.

I removed my changes to p3767.conf.common and modified these fields to point to my custom dtsi in jetson-orin-nano-devkit.conf:

PINMUX_CONFIG=“orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi”;
PMC_CONFIG=“orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default.dtsi”;

Here is the updated one: jetson-orin-nano-devkit_confg.txt (4.2 KB). I have noticed that it includes orin-jetson-orin-nano-nx-pinmux-dp-gpio-default.dtsi at the top of the file wich is stored in JetPack_5.1.5_L…NANO_TARGETS/Linux_for_Tegra/bootloader/.

I still don’t see the changes applied in the live dtb running on the system: live.txt (427.9 KB). I have also checked the dtb in the boot folder that the system is supposedly running: [ 0.002348] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/kernel-5.10/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t23x/p3768/kernel-dts/tegra234-p3767-0003-p3768-0000-a0.dts. For which I decompiled /boot/dtb/kernel_tegra234-p3767-0003-p3768-0000-a0.dtb and I don’t see my custom pinmux there either.

Is there anything else that may be overriding my custom dtsi files anywhere else?

It is expected as the pinmux/gpio dtsi are loaded by MB1 rather than kernel.
As a result, they are not part of kernel-dtb.

Please check the flash log to confirm the updated pinmux dtsi(i.e. orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi) has been used.

And you can simply run the following command for their pinmux register before and after you apply the pinmux change.

// SPI1_SCK
$ sudo busybox devmem 0x0243d028
// SPI1_MISO
$ sudo busybox devmem 0x0243d018
// SPI1_MOSI
$ sudo busybox devmem 0x0243d040
// SPI1_CS0
$ sudo busybox devmem 0x0243d008
// SPI1_CS1
$ sudo busybox devmem 0x0243d038

I didn’t notice instructions on how to modify the kernel dtb. Funny I saw a refrence to that the kernel might be overriding mb1. I tried decompiling the .dtb dfile in /boot/dtb, which is the main one that the system is using, modifying it, then recompilling it and overriding it. But the live dts I decompile still doesn’t have my changes. That’s when I switched to doing the excel sheet, but I’m kind of back to square one trying to get the kernel to take my changes.

Yeap, it’s using the one that was generated by the excel sheet except for gpioint-config. I see those .dtsi files show up in two areas of the flash log. The gpioint-config points to the default tegra one when I’ve included the one generated by the excel sheet in the orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi file using this: “include “./orin-jetson-orin-nano-nx-pinmux-dp-gpio-default.dtsi”/

I’ve included the full log if you wanted to see it.

terminal log.txt (91.1 KB)

Block1

Copy /home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/kernel/dtb/tegra234-p3767-0003-p3768-0000-a0.dtb to /home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/kernel/dtb/tegra234-p3767-0003-p3768-0000-a0.dtb.rec
Generated UUID e8128943-c92b-4394-8e7a-82096ce96b89 for mounting root APP partition.
copying bctfile(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-p3767-0001-sdram-l4t.dts)… done.
copying minratchet_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-ratchet-p3767-0000.dts)… done.
copying device_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-device-p3767-0000.dts)… done.
copying misc_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-misc-p3767-0000.dts)… done.
copying pinmux_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi)… done.
copying gpioint_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts)… done.
copying pmic_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-pmic-p3767-0000-a02.dts)… done.
copying pmc_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default.dtsi)… done.
copying deviceprod_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-cprod-p3767-0000.dts)… done.
copying prod_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-prod-p3767-0000.dts)… done.
copying scr_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb2-bct-scr-p3767-0000.dts)… done.
copying wb0sdram(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-p3767-0001-wb0sdram-l4t.dts)… done.
copying bootrom_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb1-bct-reset-p3767-0000.dts)… done.
Existing uphylane_config(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/tegra234-mb1-bct-uphylane-si.dtsi) reused.
copying dev_params(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-br-bct-p3767-0000-l4t.dts)… done.
copying dev_params_b(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-br-bct_b-p3767-0000-l4t.dts)… done.
copying mb2bct_cfg(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/t186ref/BCT/tegra234-mb2-bct-misc-p3767-0000.dts)… done.
Existing pscfwfile(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/pscfw_t234_prod.bin) reused.
Existing pscbl1file(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/psc_bl1_t234_prod.bin) reused.
Existing mtsmcefile(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/mce_flash_o10_cr_prod.bin) reused.
Existing mb2applet(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/applet_t234.bin) reused.
Existing bootloader(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/mb2_t234.bin) reused.
copying initrd(/home/galaxia/nvidia/nvidia_sdk/JetPack_5.1.5_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/bootloader/l4t_initrd.img)… done.

Block 2

./tegraflash.py --bl uefi_jetson_with_dtb.bin --odmdata gbe-uphy-config-8,hsstp-lane-map-3,hsio-uphy-config-0 --overlay_dtb L4TConfiguration.dtbo,tegra234-p3767-overlay.dtbo,tegra234-p3768-overlay.dtbo, --bldtb tegra234-p3767-0003-p3768-0000-a0.dtb --applet mb1_t234_prod.bin --cmd “flash; reboot” --cfg flash.xml --chip 0x23 --concat_cpubl_bldtb --cpubl uefi_jetson.bin --minratchet_config tegra234-mb1-bct-ratchet-p3767-0000.dts --device_config tegra234-mb1-bct-device-p3767-0000.dts --misc_config tegra234-mb1-bct-misc-p3767-0000.dts –pinmux_config orin-jetson-orin-nano-nx-pinmux-dp-pinmux.dtsi –gpioint_config tegra234-mb1-bct-gpioint-p3767-0000.dts --pmic_config tegra234-mb1-bct-pmic-p3767-0000-a02.dts –pmc_config orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default.dtsi --deviceprod_config tegra234-mb1-bct-cprod-p3767-0000.dts --prod_config tegra234-mb1-bct-prod-p3767-0000.dts --scr_config tegra234-mb2-bct-scr-p3767-0000.dts --wb0sdram_config tegra234-p3767-0001-wb0sdram-l4t.dts --br_cmd_config tegra234-mb1-bct-reset-p3767-0000.dts --uphy tegra234-mb1-bct-uphylane-si.dtsi --dev_params tegra234-br-bct-p3767-0000-l4t.dts,tegra234-br-bct_b-p3767-0000-l4t.dts --mb2bct_cfg tegra234-mb2-bct-misc-p3767-0000.dts --bins “psc_fw pscfw_t234_prod.bin; mts_mce mce_flash_o10_cr_prod.bin; mb2_applet applet_t234.bin; mb2_bootloader mb2_t234.bin; xusb_fw xusb_t234_prod.bin; dce_fw display-t234-dce.bin; nvdec nvdec_t234_prod.fw; bpmp_fw bpmp_t234-TE950M-A1_prod.bin; bpmp_fw_dtb tegra234-bpmp-3767-0003-3509-a02.dtb; sce_fw camera-rtcpu-sce.img; rce_fw camera-rtcpu-t234-rce.img; ape_fw adsp-fw.bin; spe_fw spe_t234.bin; tos tos-optee_t234.img; eks eks_t234.img” --sdram_config tegra234-p3767-0001-sdram-l4t.dts --cust_info custinfo_out.bin --ramcode 2 --bct_backup --boot_chain A

I also noticed this section talking about parsing the dtsi files, seems ok to me except for a warning:

[ 5.5212 ] MB1-BCT version: 0.13

[ 5.5231 ] Parsing config file :orin-jetson-orin-nano-nx-pinmux-dp-pinmux_cpp.dtb
[ 5.5236 ] Added Platform Config 0 data with size :- 2384

[ 5.5259 ] Parsing config file :orin-jetson-orin-nano-nx-pinmux-dp-padvoltage-default_cpp.dtb
[ 5.5263 ] WARNING: unknown node ‘g2’
[ 5.5265 ] WARNING: unknown node ‘g2’
[ 5.5265 ] WARNING: unknown node ‘g9’
[ 5.5265 ] WARNING: unknown node ‘g9’
[ 5.5265 ] Added Platform Config 2 data with size :- 24

I realized what you meant, the kernel doesn’t affect the pinmux so that’s why I wouldnt’ see it in the kernel dtb. When I run cat /sys/kernel/debug/pinctrl/*/pinmux-pins I can see that the SPI1 pins are unbclaimed which is why I believe that my pinmux is not being applied.

pin 133 (SPI1_SCK_PZ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 134 (SPI1_MISO_PZ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 135 (SPI1_MOSI_PZ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 136 (SPI1_CS0_PZ6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 137 (SPI1_CS1_PZ7): (MUX UNCLAIMED) (GPIO UNCLAIMED)

You have to confirm that the FDT has been specified in /boot/extlinux/extlinux.conf or the DTB will not be loaded from /boot/dtb/kernel_XXX.dtb.

Correct, please simply run the busybox devmem to check if the value of related pinmux registers have been updated.

This one is found in Linux_for_Tegra/rootfs/boot/extlinux/ extlinux.txt (857 Bytes). I see that FDT /boot/dtb/kernel_tegra234-p3767-0003-p3768-0000-a0.dtb is included.

I see that the values of devmem have changed:

g_nano@tegra-ubuntu:~$ sudo busybox devmem 0x0243d028
[sudo] password for g_nano:
0x00001404
g_nano@tegra-ubuntu:~$ sudo busybox devmem 0x0243d018
0x00000454
g_nano@tegra-ubuntu:~$ sudo busybox devmem 0x0243d040
0x00000404
g_nano@tegra-ubuntu:~$ sudo busybox devmem 0x0243d008
0x00000458
g_nano@tegra-ubuntu:~$ sudo busybox devmem 0x0243d038
0x00000059

The old one:

root@tegra-ubuntu:/sys/kernel/debug/pinctrl# busybox devmem 0x0243d028
0x00001055
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d018
0x00000055
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d040
0x00000055
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d008
0x00000059
root@tegra-ubuntu:/sys/kernel/debug/pinctrl# sudo busybox devmem 0x0243d038
0x00000059

Does the new one look correct? Where do you get the values from to make sure they look “ok”?

I tried outputting some data over spidev0.0 and there’s still nothing coming out, the CS pins aren’t being held high either. That would be my spi1 in the device tree that I’m trying to get working.

Yes, they look good to me.
Let me take 0x0243d028(for SPI1_SCK) as example.
Please search for PADCTL_G2_SPI1_SCK_0 from Orin TRM document and you could find the following:
Bit 0:1 should be 0 as SPI1 and Bit 10 should be 1 as SFIO for SPI usage.


Please share the full dmesg and the command you run to verify /dev/spidev0.0 for further check.