Change the device tree for DisplayPort on DP1?

WayneWWW · April 28, 2021, 9:49am

Hi,

I just have time to review the whole device tree again…

Why did you put hdmi-display under sor1 to okay and dp-display to disabled…??

sor1 {
compatible = “nvidia,tegra210-sor1”;
reg = <0x0 0x54580000 0x0 0x40000>;
reg-names = “sor”;
interrupts = <0x0 0x4c 0x4>;
status = “okay”;
nvidia,sor-ctrlnum = <0x1>;
nvidia,dpaux = <0x75>;
nvidia,xbar-ctrl = <0x0 0x1 0x2 0x3 0x4>;
clocks = <0x26 0x16f 0x26 0xde 0x26 0x16e 0x26 0xb7 0x26 0x12f 0x26 0xf3 0x26 0xca 0x26 0x7d 0x26 0x6f 0x26 0x80>;
clock-names = “sor1_ref”, “sor_safe”, “sor1_pad_clkout”, “sor1”, “pll_dp”, “pll_p”, “maud”, “hda”, “hda2codec_2x”, “hda2hdmi”;
resets = <0x26 0xb7 0x26 0x7d 0x26 0x6f 0x26 0x80>;
reset-names = “sor1”, “hda_rst”, “hda2codec_2x_rst”, “hda2hdmi_rst”;
nvidia,ddc-i2c-bus = <0x76>;
nvidia,hpd-gpio = <0x5b 0xe1 0x1>;
nvidia,active-panel = <0x77>;
linux,phandle = <0x6a>;
phandle = <0x6a>;

		hdmi-display {
			compatible = "hdmi,display";
			status = "okay";
			generic-infoframe-type = <0x87>;
			linux,phandle = <0x77>;
			phandle = <0x77>;

			disp-default-out {
				nvidia,out-xres = <0x1000>;
				nvidia,out-yres = <0x870>;
				nvidia,out-type = <0x1>;
				nvidia,out-flags = <0x2>;
				nvidia,out-parent-clk = "pll_d2";
				nvidia,out-align = <0x0>;
				nvidia,out-order = <0x0>;
			};
		};

		dp-display {
			compatible = "dp, display";
			status = "disabled";
			linux,phandle = <0x119>;
			phandle = <0x119>;
		};

ElectronicSystems · April 28, 2021, 10:04am

No, this is the original DEVKIT!!! .dts → to compare

This is my BOARD.dts !!! dts_output_221-04-22.txt (326,5 KB)

WayneWWW · April 28, 2021, 10:06am

You don’t need to post such thing here. We have the original code.

ElectronicSystems · April 28, 2021, 10:07am

Okay, sorry

ElectronicSystems · April 28, 2021, 10:14am

This is my current board .dts file →

output_28.04.2021_12.09.txt (326.5 KB)

WayneWWW · April 28, 2021, 10:19am

Any difference between this one and that 4/22 one?

ElectronicSystems · April 28, 2021, 10:24am

Only one small difference, but also brings nothing…

Trumany · April 28, 2021, 12:08pm

Hi, please make sure the lane mapping is correct on your design, the lane0 is swapped with lane2 with DP configuration as below which is different to HDMI setting.

ElectronicSystems · April 28, 2021, 1:13pm

Hi,

thank you for the answer.
Our DP1 is connected like this:

Is then <0 1 2 3 4> wrong ?

Trumany · April 30, 2021, 12:36am

It’s correct. Can you share a screenshot of your own schematic of this part?

ElectronicSystems · April 30, 2021, 10:50am

I am very happy to do this, but only to you privately

Trumany · April 30, 2021, 12:20pm

Your schematic looks fine. Then it looks like a pure software problem. @WayneWWW will continue debugging from sw side.

ElectronicSystems · April 30, 2021, 12:26pm

Thank you very much!

I think so too…

ElectronicSystems · May 1, 2021, 8:59am

What I also keep wondering is why on the DEVKIT the nvidea,hpd-gpio is also TEGRA_GPIO(CC,1)???

Original tegra210-dp.dtsi file for the devkit:

The nvidea,hpd-gpio connector is on the DEVKIT for the DP but at TEGRA_GPIO(CC,6) ???

WayneWWW · May 1, 2021, 12:06pm

Just a weird try, what will happen if you toggle the CC6 gpio through the gpio sysfs when DP cable connected? Will anything come out in dmesg?

ElectronicSystems · May 1, 2021, 1:21pm

I have done, but nothing happens…

I don’t understand why TEGRA_GPIO(CC,1) is always queried for DP or HDMI ???.

FOR HDMI = SOR1:
Original tegra210-ers-hdmi-e2190-1100-a00.dtsi file for the devkit:

FOR DP = SOR:
Original tegra210-dp.dtsi file for the devkit:

the devkit schematic shows it again:

This is then TEGRA_GPIO (CC, 1) and TEGRA_GPIO (CC, 6) ??? and not both TEGRA_GPIO (CC, 1) ???

WayneWWW · May 1, 2021, 2:11pm

I guess the nvidia,hpd-gpio in the DT of dp port is not in use at all. But need to check the driver…

You can also compile the kernel code and add some debug print to track this function on devkit. Then, again compare the the result on your board.

ElectronicSystems · May 1, 2021, 6:06pm

Exactly, the nvidia,hpd-gpio is not used with DP

Okay, I will keep looking for problems…

I am curious when it finally runs

ElectronicSystems · May 1, 2021, 6:17pm

Did you notice anything else in the current .dts → output_28.04.2021_12.09.txt file

WayneWWW · May 3, 2021, 2:41am

Hi,

Please check below node and share the result.

root@nvidia-desktop:/sys/kernel/debug# cat tegra_dpX/dpaux_regs #X could be 0,1…