Jetson nano sor1 DP Setting NG

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

Hi,
I’m currently using the jetson nano develop kit and I’m trying to set up HDMI as DP.
(tegra-p3448-0000-p3449-0000-b00.dtb)
What I modified was after uploading the image in the tutorial to SDCARD, I changed boot/dtb to dts.
In the source, sor1 was changed to the following and connected to FDT boot/dtb/new.dtb.
I confirmed that it is set to DP-0 and DP-1 in xrandr, and now when I connect the DP port to another carrier board, there is no output. Can you tell me what part I am missing?

sor1 {
compatible = “nvidia,tegra210-sor1”;
reg = <0x0 0x54580000 0x0 0x40000>;
reg-names = “sor”;
interrupts = <0x0 0x4c 0x4>;
status = “okay”;
nvidia,sor-ctrlnum = <0x1>;
nvidia,dpaux = <0x75>;
nvidia,xbar-ctrl = <0x0 0x1 0x2 0x3 0x4>;
clocks = <0x26 0x16f 0x26 0xde 0x26 0x16e 0x26 0xb7 0x26 0x12f 0x26 0xf3 0x26 0xca 0x26 0x7d 0x26 0x6f 0x26 0x80>;
clock-names = “sor1_ref”, “sor_safe”, “sor1_pad_clkout”, “sor1”, “pll_dp”, “pll_p”, “maud”, “hda”, “hda2codec_2x”, “hda2hdmi”;
resets = <0x26 0xb7 0x26 0x7d 0x26 0x6f 0x26 0x80>;
reset-names = “sor1”, “hda_rst”, “hda2codec_2x_rst”, “hda2hdmi_rst”;
nvidia,ddc-i2c-bus = <0x76>;
nvidia,hpd-gpio = <0x5b 0xe1 0x1>;
nvidia,active-panel = <0x77>;
nvidia,sor1-output-type = “dp”;
linux,phandle = <0x6a>;
phandle = <0x6a>;

		hdmi-display {
			compatible = "hdmi,display";
			status = "disabled";
			generic-infoframe-type = <0x87>;
			linux,phandle = <0x104>;
			phandle = <0x104>;

			disp-default-out {
				nvidia,out-xres = <0x1000>;
				nvidia,out-yres = <0x870>;
				nvidia,out-type = <0x1>;
				nvidia,out-flags = <0x2>;
				nvidia,out-parent-clk = "pll_d2";
				nvidia,out-align = <0x0>;
				nvidia,out-order = <0x0>;
			};
		};

		dp-display {
			compatible = "dp, display";
			status = "okay";
			nvidia,hpd-gpio = <0x5b 0xe1 0x1>;
			nvidia,is_ext_dp_panel = <0x1>;
			linux,phandle = <0x77>;
			phandle = <0x77>;

			disp-default-out {
				nvidia,out-type = <0x3>;
				nvidia,out-align = <0x0>;
				nvidia,out-order = <0x0>;
				nvidia,out-flags = <0x0>;
				nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
				nvidia,out-parent-clk = "pll_d2_out0";
			};

			dp-lt-settings {

				lt-setting@0 {
					nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
					nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
					nvidia,tx-pu = <0x0>;
					nvidia,load-adj = <0x3>;
				};

				lt-setting@1 {
					nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
					vidia,post-cursor = <0x0 0x0 0x0 0x0>;
					nvidia,tx-pu = <0x0>;
					nvidia,load-adj = <0x4>;
				};

				lt-setting@2 {
					nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
					nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
					nvidia,tx-pu = <0x0>;
					nvidia,load-adj = <0x6>;
				};
			};
		};

		prod-settings {
			#prod-cells = <0x3>;
			prod_list_hdmi_soc = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_111m", "prod_c_hdmi_111m_223m", "prod_c_hdmi_223m_300m", "prod_c_hdmi_300m_600m";
			prod_list_hdmi_board = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_75m", "prod_c_hdmi_75m_150m", "prod_c_hdmi_150m_300m", "prod_c_hdmi_300m_600m";

			prod {
				prod = <0x3a0 0x1 0x1 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x300f80 0x68 0xf000000 0xe000000 0x138 0xffffffff 0x3c3c3c3c 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
			};

			prod_c_hdmi_0m_54m {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x5000310 0x60 0xf01f00 0x1100 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x2d2f2f2f 0x148 0xffffffff 0x0 0x170 0xf040ff00 0x80406600>;
			};

			prod_c_hdmi_54m_111m {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
			};

			prod_c_hdmi_111m_223m {
				prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
			};

			prod_c_hdmi_223m_300m {
				prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
			};

			prod_c_hdmi_300m_600m {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x5000310 0x60 0xf01f00 0x300f00 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x30353537 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406000>;
			};

			prod_c_54M {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
			};

			prod_c_75M {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
			};

			prod_c_150M {
				prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
			};

			prod_c_300M {
				prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
			};

			prod_c_600M {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
			};

			prod_c_dp {
				prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
			};

			prod_c_hdmi_54m_75m {
				prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x5000310 0x60 0xf01f00 0x301500 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x2d303030 0x148 0xffffffff 0x0 0x170 0xf040ff00 0x80406600>;
			};

			prod_c_hdmi_75m_150m {
				prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x309300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x2d303030 0x148 0xffffffff 0x0 0x170 0xf040ff00 0x80406600>;
			};

			prod_c_hdmi_150m_300m {
				prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x309300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x2d303430 0x148 0xffffffff 0x0 0x170 0xf040ff00 0x80406600>;
			};
		};
	};
3

Based on my experience, it is pinmux setting problem. Your hpd pin is probably still GPIO but not SFIO.

4

The existing sor1 is set to hdmi, and as I understand it is being used as hpd, the same as dp, so I did not modify it separately, but it appears that HPD and aux settings were made.
Is there anything different about the DTS I changed?

test.dts.zip (40.8 KB)

5

Hi,

HDMI is using hpd pin as GPIO. When you use that for DP, you have to configure it for SFIO.
It is very easy to set to a GPIO.
You have to use the pinmux spreadsheet to make it correct.

If you don’t know what I am talking about, please also tell.

6

스크린샷 2024-02-01 오전 10.27.13

image
image2184×264 66 KB

Thank you for your kind notice.

I’m leaving a screenshot to make sure my understanding is correct.

If you set it up like in the spreadsheet above, isn’t that function set to DP?
It seems that nvidia,function = “dp”;

7

Could you check this post and dump the same node before and after you hotplug the DP cable?

I would like to know if you see any value got changed in below node when doing hotplug.
image

If it does not change, please dump the register with address 0x6000D700.

8

It is being read identically to the screenshot you sent.
Then I don’t understand the recommended method. Can you explain in more detail about dumping 0x6000D700?

I’ve read other parts like the forum above, but I haven’t figured out exactly what it means yet.

  1. busybox devmem 0x60006280
    → 0x03200780
  2. busybox devmem 0x6000628c
    → 0x01042009
  3. busybox devmem 0x60006298
    → 0x40048340
  4. busybox devmem 0x600062a4
    → 0x0FE11099

Please let me know if there is anything I’m missing. Thank you as always!

9

You can try to google search what is devmem doing first. And then combine it with 0x6000D700 and share me the result.

Also, I am not talking about just read my screenshot. I am asking when you insert the DP cable and not insert the DP cable, will those register info dumped from that node dpaux_regs be different or not.
If there is no change, it means hotplug still does not take effect.

BTW, if you have more than two DP nodes in use, please only enable the problematic one for now because we are doing debug. I don’t want you to read the wrong node.
For example, there could be tegra_dp0 and tegra_dp1 node at same time if you enable two heads DP all at once.

10

Okay, I’ll review the information you shared and get back to you

11

sorry for one typo that I use HDMI instead of DP in previous comment. Corrected to use DP.

13

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