Dual display: HDMI + DP

ShayWang · March 21, 2017, 8:14am

I want to set up dual display on TX1 and I have already prepared the hardware. I know by default the HDMI is ON and works fine on my carrier board. But DP does not work. I know some changes should be made in the dts files, but I couldn’t find any official documents about this issue. Any help would be appreciated. Tks:)

HDMI ports: E36, E35, D37, D36, C38, C37, E39, E38, A35, A34, A33.
DP ports: H36, H35, G37, G36, F38, F37, H39, H38, B35, B34, B36.
L4T version: R24.2.1
.conf file: p2371-2180-devkit.conf
dtb file: tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb

Cill · March 21, 2017, 9:19am

I’m pretty new in NVIDIA development. Can someone tell if I’m not wrong ?

According the TRM (the reference manual) .pdf part 27.3.2, you need to activate Aux channel and HPD (hot plug detection). “dpaux” are disabled by default.

***AUXDISPLAY :

There’s some part you need to activate in the dts “tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb”.

	dpaux {
		compatible = "nvidia,tegra210-dpaux";
		reg = <0x0 0x545c0000 0x0 0x40000>;
		interrupts = <0x0 0x9f 0x4>;
		status = "okay"; // before status = "disabled"
	};

	dpaux1 {
		compatible = "nvidia,tegra210-dpaux1";
		reg = <0x0 0x54040000 0x0 0x40000>;
		interrupts = <0x0 0xb 0x4>;
		status = "okay"; // before status = "disabled"
	};

compile your new dtb.

Then you need to activate the AUXDISPLAY in your kernel as well :
make menuconfig => Device Drivers => Auxiliary Display support

Then, compile the kernel
(Compiling Tegra X1/X2 source code - RidgeRun Developer Connection)

.dtb and Image must be in the /boot of your TX1.

**HPD:

mmmmh… I don’t understand this part the node sor and common in the dtb (can’t say wich one to use)

I say all this but I didn’t try it myself.

linuxdev · March 21, 2017, 2:39pm

I can’t answer your specific question, but you may find some information on editing dtb files useful. The various device tree source files (dts) are available in the kernel source and end up producing a device tree blob (binary) file going in “/boot/”, but you can reverse compile the existing dtb to dts, edit, and convert that back to dtb. The particular dtb used is named in the “FDT” key/value pair of “/boot/extlinux/extlinux.conf”.

Reverse compiling a binary dtb to dts:

dtc -I dtb -O dts -o /tmp/extracted.dts /boot/the_firmware_in_extlinux.dtb
# ...edit or explore the dts...

Re-compiling a dts into dtb:

dtc -I dts -O dtb -o /tmp/modified.dtb /tmp/extracted.dts

NOTE: dtc is available as an ordinary package, or from within the kernel source as a compile target.

WayneWWW · March 22, 2017, 9:47am

Hi ShayWang,

We provide a sample for eDP that may help your dp case.

The dts is kernel/arch/arm64/boot/dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts

ShayWang · March 28, 2017, 2:59am

Thanks @WayneWWW, is there any reference material that can help me adapt this eDP.dts to my DP case?

WayneWWW · March 28, 2017, 5:34am

Hi ShayWang,

This patch is for dp. I hope this could help you.

Subject: [PATCH] Changes to enable DP on TX1

To enable external DP monitor on sor0, changes
have been done in the required dts & dtsifiles.

---

diff --git a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index dc24ce8..5ad10b3 100644
--- a/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -30,6 +30,7 @@
 #include "panel-s-edp-uhdtv-15-6.dtsi"
 #include "panel-s-wqxga-10-1.dtsi"
 #include "tegra210-platforms/tegra210-ers-hdmi-e2190-1100-a00.dtsi"
+#include "tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi"
 #include "tegra210-platforms/tegra210-sdhci.dtsi"
 #include "tegra210-platforms/tegra210-p2180-common.dtsi"
 #include "tegra210-platforms/tegra210-thermal-fan-est-p2530-0930.dtsi"
@@ -260,6 +261,7 @@
 			nvidia,cmu-enable = <1>;
 			nvidia,fb-bpp = <32>; /* bits per pixel */
 			nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
+			nvidia,dc-or-node = "/host1x/sor";
 		};
 
 		dsi {
@@ -284,6 +286,7 @@
 		};
 
 		sor {
+			status = "okay";
 			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 6) 0>; /* PCC6 */
 			panel-s-edp-uhdtv-15-6 {
 				nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0>; /* PV0 */
@@ -302,6 +305,9 @@
 		vi {
 			status = "okay";
 		};
+		dpaux {
+			status = "okay";
+		};
 	};
 
 	serial@70006040 {
diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi
index ee5310e..7284fc4 100644
--- a/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi
@@ -1,7 +1,7 @@
 /*
  * arch/arm/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi
  *
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,11 +22,13 @@
 
 / {
 	host1x {
-		sor1 {
+		sor {
+			nvidia,sor1-output-type = "dp";
 			dp-display {
 				status = "okay";
 				compatible = "dp, display";
 				nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 1>; /* PN7 */
+				nvidia,is_ext_dp_panel = <1>;
 				disp-default-out {
 					nvidia,out-type = <TEGRA_DC_OUT_DP>;
 					nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
diff --git a/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi b/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi
index d65063a..91c4662 100644
--- a/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi
+++ b/arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi
@@ -345,6 +345,12 @@
 			vdd_ds_1v8-supply  = <&en_dvdd_disp_1v8>;
 			avdd_io_edp-supply = <&max77620_gpio7>;
 		};
+		dc@54240000 {
+			vdd-dp-pwr-supply = <&vdd_3v3>;
+			avdd-dp-pll-supply = <&max77620_sd3>;
+			vdd-edp-sec-mode-supply = <&max77620_gpio7>;
+			vdd-dp-pad-supply = <&en_dvdd_disp_1v8>;
+                };
 
 		i2c@546c0000 {
 			bus-pullup-supply = <&max77620_sd3>;

ShayWang · March 28, 2017, 5:41am

Hi @WayneWWW, let me try this first and get back to you. Tks.

ShayWang · March 30, 2017, 4:52am

Hi @WayneWWW, I have tried your reply, I modified the three files you mentioned:

arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi
arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi

The result is HDMI works fine and DP does not work, nothing output from DP.

Besides these three dts/dtsi files, is there any other changes should be made to implement this dual display?

And in your reply Line 65 nvidia,sor1-output-type = “dp”;
, is this right? I think sor0 is for DP, and sor1 is for HDMI. My hardware connections are as follows:

HDMI ports:

A33 --- HPD
A34 --- SDA
A35 --- SCL
B33 --- CEC
E35 --- CK-
E36 --- CK+
D36 --- D0-
D37 --- D0+
C37 --- D1-
C38 --- D1+
E38 --- D2-
E39 --- D2+

DP ports:

B36 --- HPD
B35 --- AUX CH+
B34 --- AUX CH-
H36 --- D3+
H35 --- D3-
G37 --- D2+
G36 --- D2-
F38 --- D1+
F37 --- D1-
H39 --- D0+
H38 --- D0-

WayneWWW · March 30, 2017, 7:27am

Hi ShayWang,

According to TRM, we support eDP on SOR0 and HDMI/DP on SOR1. As a result, TX1 cannot support dual HDMI+DP.

ShayWang · March 30, 2017, 7:39am

Hi WayneWWW,

But according to JetsonTX1_OEM_Product_DesignGuide.pdf
, page 33, “The eDP interface can also be used for DP”.

changqian9 · March 30, 2017, 9:18am

Hi WayneWWW，

I found this in a PPT from a TX1 discussion group，I thought that there DP+HDMI dual display can work on TX1. Did I misunderstand the PPT or maybe there is another way to implement this?

Thanks!

Trumany · March 31, 2017, 4:14am

Generally eDP port can be used as DP port as they are almost same in hardware. But for TX1, eDP block is limited to only support local panels and not support an external DP port, and so if use eDP as DP, there will be no audio and no HDCP.

ShayWang · March 31, 2017, 6:23am

Thanks @Trumany, we don’t need audio and HDCP, could you please provide some info for us to set up this dual display, i.e. DP on SOR0 and HDMI on SOR1?

WayneWWW · April 5, 2017, 4:46am

Hi @WayneWWW, I have tried your reply, I modified the three files you mentioned:

arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts

arch/arm64/boot/dts/tegra210-platforms/tegra210-ers-dp-e2220-1170-a00.dtsi

arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi

The result is HDMI works fine and DP does not work, nothing output from DP.

Besides these three dts/dtsi files, is there any other changes should be made to implement this dual display?

And in your reply Line 65 nvidia,sor1-output-type = “dp”;
, is this right? I think sor0 is for DP, and sor1 is for HDMI. My hardware connections are as follows:

HDMI ports:

A33 --- HPD

A34 --- SDA

A35 --- SCL

B33 --- CEC

E35 --- CK-

E36 --- CK+

D36 --- D0-

D37 --- D0+

C37 --- D1-

C38 --- D1+

E38 --- D2-

E39 --- D2+

DP ports:

B36 --- HPD

B35 --- AUX CH+

B34 --- AUX CH-

H36 --- D3+

H35 --- D3-

G37 --- D2+

G36 --- D2-

F38 --- D1+

F37 --- D1-

H39 --- D0+

H38 --- D0-

Hi ShayWang,

After quick check, the “sor1-output-type” does not influence the actual sor that dp is using.

You can take a look at board-panel.c. The function “tegra_seconrday_panel_get_dt_node” is where we check the secondary panel and it is usually SOR1 that dp is attached. As a result, “sor1-output-type” is just a string used to find dp. It does not imply you are using SOR1 with dp.