How to change the HDMI to DP on R32.2 release

michaelwei9pt6c · August 28, 2019, 9:31am

Hi,

I have a carrier board for TX1 module that changed the HDMI to DP, so I would like to change the HDMI to DP on R32.2 and modified the codes as below:

Change the pinmux:

hdmi_int_dp_hpd_pcc1 {
    				nvidia,pins = "hdmi_int_dp_hpd_pcc1";
    -				nvidia,function = "rsvd1";
    +				nvidia,function = "dp";
    				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
    				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    				nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
    };

Modified the the device tree as below:

/* tegradc.1 */
   dc@54240000 {
        	status = "okay";
		nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
		nvidia,emc-clk-rate = <300000000>;
		nvidia,cmu-enable = <1>;
		nvidia,fb-bpp = <32>; /* bits per pixel */
		nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
		nvidia,dc-or-node = "/host1x/sor1";
		nvidia,dc-connector = <&sor1>;
		win-mask = <0x7>; /* Assign only wins A/B/C */
   };

   sor1 {
			nvidia,dpaux = <0xa6>;
			compatible = "nvidia,tegra210-sor1";
			clocks = <0x41 0x16f 0x41 0xde 0x41 0x16e 0x41 0xb7 0x41 0x12f 0x41 0xf3 0x41 0xca 0x41 0x7d 0x41 0x6f 0x41 0x80>;
			resets = <0x41 0xb7 0x41 0x7d 0x41 0x6f 0x41 0x80>;
			pad-names = "hdmi";
			reg-names = "sor";
			clock-names = "sor1_ref", "sor_safe", "sor1_pad_clkout", "sor1", "pll_dp", "pll_p", "maud", "hda", "hda2codec_2x", "hda2hdmi";
			nvidia,sor1-output-type = "dp";
			status = "okay";
			nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>;
			interrupts = <0x0 0x4c 0x4>;
			phandle = <0x9d>;
			nvidia,sor-ctrlnum = <0x1>;
			reg = <0x0 0x54580000 0x0 0x40000>;
			reset-names = "sor1", "hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst";
			linux,phandle = <0x9d>;
			nvidia,active-panel = <0xa7>;

			prod-settings {
				#prod-cells = <0x3>;
				status = "okay";
				prod_list_hdmi_soc = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_111m", "prod_c_hdmi_111m_223m", "prod_c_hdmi_223m_300m", "prod_c_hdmi_300m_600m";

				prod_c_75M {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
				};

				prod {
					prod = <0x3a0 0x1 0x1 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
				};

				prod_c_hdmi_111m_223m {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_hbr2 {
					prod = <0x60 0xf00000 0x600000>;
				};

				prod_c_rbr {
					prod = <0x60 0xf00000 0x300000>;
				};

				prod_c_hdmi_223m_300m {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
				};

				prod_c_hdmi_0m_54m {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
				};

				prod_c_hbr {
					prod = <0x60 0xf00000 0x400000>;
				};

				prod_c_600M {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_300M {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
				};

				prod_c_54M {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
				};

				prod_c_hdmi_54m_111m {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
				};

				prod_c_150M {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_hdmi_300m_600m {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_dp {
					prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
				};
			};

			hdmi-display {
				compatible = "hdmi,display";
				status = "disabled";
				phandle = <0x185>;
				linux,phandle = <0x185>;

				disp-default-out {
					status = "disabled";
				};
			};

			dp-display {
				compatible = "dp, display";
				nvidia,is_ext_dp_panel = <0x1>;
				nvidia,tx-pu-disable = <0x1>;
				status = "okay";
				phandle = <0xa7>;
				linux,phandle = <0xa7>;
				nvidia,hpd-gpio = <0x82 0xe1 0x0>;

				disp-default-out {
					nvidia,out-align = <0x0>;
					nvidia,out-parent-clk = "pll_dp";
					nvidia,out-order = <0x0>;
					nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
					nvidia,out-flags = <0x0>;
					nvidia,out-type = <0x3>;
				};

				dp-lt-settings {

					lt-setting@2 {
						nvidia,load-adj = <0x6>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};

					lt-setting@0 {
						nvidia,load-adj = <0x3>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};

					lt-setting@1 {
						nvidia,load-adj = <0x4>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};
				};
			};
		}; 

   dpaux1 {
	status = "okay";
   };

I could not see the output on DP port after changed the device tree on our board. Then I tarced the codes and found that the dpaux1 DPAUX_DP_AUXSTAT was always zero.
I do not know why the dpaux1 DPAUX_DP_AUXSTAT is alway zero, please give me some advice, Thanks.

Best Regards,
Michael

WayneWWW · August 29, 2019, 6:59am

Hi Michael,

Actually you could refer to the device tree of jetson nano. It enables a DP port on SOR0 and it is TX1 based.

michaelwei9pt6c · August 29, 2019, 10:07am

Hi WayneWWW,

Thanks for your replay, I already enabled a eDP port on SOR0 and then that is working.
I also refer the nano and TX1 SOR0 device tree to modified the TX1 SOR1 device tree.
Unfortunately, the result is that the DP port on SOR1 did not work.
I found the fail reason is that the dpaux1 DPAUX_DP_AUXSTAT is alway zero, but the dpaux works fine.
Could you give me some advice? Thanks.

Best Regards,
Michael

WayneWWW · August 29, 2019, 10:28am

Hi,

Actually we didn’t verify DP on SOR1 before. All the DP we setup is on SOR0.

May I know why do you think you need to use “pll_dp” as parent clk?

What is your current dmesg?

michaelwei9pt6c · August 30, 2019, 2:32am

Hi WayneWWW,

About pll_dp, Sorry, I did a lot of experiment in previous time, so I forget to set it back to pll_d2_out0.
But it still have same problem after I set it to pll_d2_out0. The dmesg as attachment file.

I added debug messages in tegra_dc_dp_hpd_state function and found the dpaux1 DPAUX_DP_AUXSTAT was alway zero.
If the DP work fine, the DPAUX_DP_AUXSTAT will be 10000000

I typed the following command in TX1.

cat /sys/kernel/debug/tegra_dp1/dpaux_regs

And it will show as below:
DPAUX_INTR_EN_AUX 001 00000007
DPAUX_INTR_AUX 005 00000000
DPAUX_DP_AUXADDR 029 00000000
DPAUX_DP_AUXCTL 02d 00000000
DPAUX_DP_AUXSTAT 031 00000000
DPAUX_HPD_CONFIG 03d 07d000fa
DPAUX_HPD_IRQ_CONFIG 041 000000fa
DPAUX_DP_AUX_CONFIG 045 00000190
DPAUX_HYBRID_PADCTL 049 000024c2
DPAUX_HYBRID_SPARE 04d 00000000[

Because the DPAUX_DP_AUXSTAT is the read only register. I don’t know how to make the DPAUX_DP_AUXSTAT to the right status. Please give me some suggestion, thanks.

Best Regards,
Michael

TX1_R32_DP_DMESG.txt (81.9 KB)

WayneWWW · August 30, 2019, 2:54am

Sorry, I forgot to mention that please only enable one tegradc during such debug. Otherwise the log would mix up and hard to tell which one is from tegradc0 and tegradc1.

michaelwei9pt6c · August 30, 2019, 3:25am

Hi WayneWWW,

The attachment file is the dmesg that only enable tegradc1. Please check it. Thanks.

Best Regards,
Michael
TX1_R32_DP_TEGRADC1_DMESG.txt (58 KB)

WayneWWW · August 30, 2019, 3:30am

Hi Michael,

Even link training is not starting. Could you please compare your sor and tegradc devcie tree with jetson nano sor? That is the only device tree you could refer to on rel-32.2 and tx1 based.

michaelwei9pt6c · August 30, 2019, 7:04am

Hi WayneWWW,

To modified the TX1 sor1 device tree,I already refer the Nano and TX1 sor0 device tree.

The nano DP on sor device tree as below:

sor {
			nvidia,dpaux = <0x6e>;
			compatible = "nvidia,tegra210-sor";
			clocks = <0x21 0xde 0x21 0xb6 0x21 0x12f>;
			resets = <0x21 0xb6>;
			reg-names = "sor";
			clock-names = "sor_safe", "sor0", "pll_dp";
			nvidia,sor1-output-type = "dp";
			status = "okay";
			nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>;
			phandle = <0x68>;
			nvidia,sor-ctrlnum = <0x0>;
			reg = <0x0 0x54540000 0x0 0x40000>;
			reset-names = "sor0";
			linux,phandle = <0x68>;
			nvidia,active-panel = <0x6f>;
			nvidia,sor-audio-not-supported;

			prod-settings {
				#prod-cells = <0x3>;

				prod_c_dp {
					prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
				};
			};

			hdmi-display {
				compatible = "hdmi,display";
				status = "disabled";
				phandle = <0x113>;
				linux,phandle = <0x113>;
			};

			dp-display {
				compatible = "dp, display";
				nvidia,is_ext_dp_panel = <0x1>;
				status = "okay";
				phandle = <0x6f>;
				linux,phandle = <0x6f>;
				nvidia,hpd-gpio = <0x56 0xe1 0x1>;

				disp-default-out {
					nvidia,out-align = <0x0>;
					nvidia,out-parent-clk = "pll_d_out0";
					nvidia,out-order = <0x0>;
					nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
					nvidia,out-flags = <0x0>;
					nvidia,out-type = <0x3>;
				};

				dp-lt-settings {

					lt-setting@2 {
						nvidia,load-adj = <0x6>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};

					lt-setting@0 {
						nvidia,load-adj = <0x3>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};

					lt-setting@1 {
						nvidia,load-adj = <0x4>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};
				};
			};
		};

The TX1 sor1 device tree after I modified it as below:

sor1 {
			nvidia,dpaux = <0xa6>;
			compatible = "nvidia,tegra210-sor1";
			clocks = <0x41 0x16f 0x41 0xde 0x41 0x16e 0x41 0xb7 0x41 0x12f 0x41 0xf3 0x41 0xca 0x41 0x7d 0x41 0x6f 0x41 0x80>;
			resets = <0x41 0xb7 0x41 0x7d 0x41 0x6f 0x41 0x80>;
			reg-names = "sor";
			clock-names = "sor1_ref", "sor_safe", "sor1_pad_clkout", "sor1", "pll_dp", "pll_p", "maud", "hda", "hda2codec_2x", "hda2hdmi";
			nvidia,sor1-output-type = "dp";
			status = "okay";
			nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>;
			interrupts = <0x0 0x4c 0x4>;
			phandle = <0x9d>;
			nvidia,sor-ctrlnum = <0x1>;
			reg = <0x0 0x54580000 0x0 0x40000>;
			reset-names = "sor1", "hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst";
			nvidia,ddc-i2c-bus = <0xa7>;
			linux,phandle = <0x9d>;
			nvidia,hpd-gpio = <0x82 0xe1 0x1>;
			nvidia,active-panel = <0xa8>;
			nvidia,sor-audio-not-supported;

			prod-settings {
				bootloader-use-legacy-prods;
				#prod-cells = <0x3>;
				status = "okay";
				prod_list_hdmi_soc = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_111m", "prod_c_hdmi_111m_223m", "prod_c_hdmi_223m_300m", "prod_c_hdmi_300m_600m";
				prod_list_hdmi_board = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_75m", "prod_c_hdmi_75m_150m", "prod_c_hdmi_150m_300m", "prod_c_hdmi_300m_600m";

				prod_c_75M {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
				};

				prod {
					prod = <0x3a0 0x1 0x1 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
				};

				prod_c_hdmi_111m_223m {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_hbr2 {
					prod = <0x60 0xf00000 0x600000>;
				};

				prod_c_rbr {
					prod = <0x60 0xf00000 0x300000>;
				};

				prod_c_hdmi_223m_300m {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
				};

				prod_c_hdmi_0m_54m {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;

					board {
						prod = <0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x301300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
					};
				};

				prod_c_hdmi_150m_300m {

					board {
						prod = <0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x301300 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
					};
				};

				prod_c_hbr {
					prod = <0x60 0xf00000 0x400000>;
				};

				prod_c_600M {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_hdmi_75m_150m {

					board {
						prod = <0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x301300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
					};
				};

				prod_c_300M {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
				};

				prod_c_54M {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
				};

				prod_c_hdmi_54m_111m {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
				};

				prod_c_150M {
					prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
				};

				prod_c_hdmi_300m_600m {
					prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;

					board {
						prod = <0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x301f00 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333e3e3e 0x148 0xffffffff 0x70707 0x170 0x40ff00 0x406600>;
					};
				};

				prod_c_hdmi_54m_75m {

					board {
						prod = <0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x301300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
					};
				};

				prod_c_dp {
					prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
				};
			};

			hdmi-display {
				compatible = "hdmi,display";
				generic-infoframe-type = <0x87>;
				status = "disabled";
				phandle = <0x187>;
				linux,phandle = <0x187>;

				disp-default-out {
					nvidia,out-xres = <0x1000>;
					nvidia,out-align = <0x0>;
					nvidia,out-parent-clk = "pll_d2";
					nvidia,out-order = <0x0>;
					status = "disabled";
					nvidia,out-flags = <0x2>;
					nvidia,out-type = <0x1>;
					nvidia,out-yres = <0x870>;
				};
			};

			dp-display {
				compatible = "dp, display";
				nvidia,is_ext_dp_panel = <0x1>;
				status = "okay";
				phandle = <0xa8>;
				linux,phandle = <0xa8>;
				nvidia,hpd-gpio = <0x82 0xe1 0x1>;

				disp-default-out {
					nvidia,out-align = <0x0>;
					nvidia,out-parent-clk = "pll_d2_out0";
					nvidia,out-order = <0x0>;
					nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
					nvidia,out-flags = <0x0>;
					nvidia,out-type = <0x3>;
				};

				dp-lt-settings {

					lt-setting@2 {
						nvidia,load-adj = <0x6>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};

					lt-setting@0 {
						nvidia,load-adj = <0x3>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};

					lt-setting@1 {
						nvidia,load-adj = <0x4>;
						nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
						nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
						nvidia,tx-pu = <0x0>;
						nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					};
				};
			};
		};

But the TX1 DP on sor1 still did not work, I did not find any wrong setting on my sor device tree.
Please give me some advice, thanks.

Best Regards,
Michael

WayneWWW · September 2, 2019, 2:53am

Hi Michael,

Is the device able to detect hotplug event?

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