Display port

Robotics & Edge Computing Jetson Systems Jetson TX1
1

Hi,

We have a custom carrier board that has a standard external display port connector.
I know the port is electrically wired correctly because I had it working with R24 but now I have upgraded to R28 and I’m having some problems.

This is the output from the kernel:

[   26.767310] tegradc tegradc.1: tegra_dc_program_mode():MODE:1920x1080@60.000Hz pclk=148500000
[   26.767313] tegradc tegradc.1: dc->mode.pclk = 148500000 clk_get_rate(dc->clk) = 19200000
[   26.767327] tegradc tegradc.1: pclk is zero!
[   26.767330] tegradc tegradc.1: tegra_dc_init: tegra_dc_program_mode failed
[   26.767410] tegradc tegradc.1: _tegra_dc_controller_enable: tegra_dc_init failed
[   26.829052] tegradc tegradc.1: tegra_dc_program_mode():MODE:1920x1080@60.000Hz pclk=148500000
[   26.829055] tegradc tegradc.1: dc->mode.pclk = 148500000 clk_get_rate(dc->clk) = 19200000
[   26.829069] tegradc tegradc.1: pclk is zero!
[   26.829071] tegradc tegradc.1: tegra_dc_init: tegra_dc_program_mode failed
[   26.829134] tegradc tegradc.1: _tegra_dc_controller_enable: tegra_dc_init failed

I think something must be wrong with my device tree setup but I can’t find it.

My device tree setup:

dc@54240000 {
            status = "okay";
            nvidia,dc-or-node = "/host1x/sor1";
            nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
            nvidia,cmu-enable = <1>;

            vdd-dp-pwr-supply = <&vdd_3v3>;
            avdd-dp-pll-supply = <&max77620_sd3>;
            vdd-edp-sec-mode-supply = <&vdd_sys_boost>;
            vdd-dp-pad-supply = <&max77620_ldo8>;
        };

        sor1 {
            status = "okay";
            nvidia,sor1-output-type = "dp";
            dp-display {
                status = "okay";
                compatible = "dp, display";
                nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 1>; /* PN7 */
                nvidia,is_ext_dp_panel = <1>;
                disp-default-out {
                        nvidia,out-type = <TEGRA_DC_OUT_DP>;
                        nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
                        nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
                        nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
                        nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
                                            TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
                                            TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
                                            TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
                        nvidia,out-parent-clk = "pll_d2";
                };
                dp-lt-settings {
                    lt-setting@0 {
                        nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
                        nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
                        nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
                        nvidia,tx-pu = <0>;
                        nvidia,load-adj = <0x3>;
                    };
                    lt-setting@1 {
                        nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
                        nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
                        nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
                        nvidia,tx-pu = <0>;
                        nvidia,load-adj = <0x4>;
                    };
                    lt-setting@2 {
                        nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
                        nvidia,lane-preemphasis = <PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1>;
                        nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
                        nvidia,tx-pu = <0>;
                        nvidia,load-adj = <0x6>;
                    };
                };
            };
        };

Any help as to why pclk is zero would be greatly appreciated.

Thanks

K.

2

Ok, so I have got around this problem by changing the out-parent-clk

sor1 {
           dp-display {
                disp-default-out {
                        nvidia,out-parent-clk = "pll_d2_out0";

But now I encounter this problem:

[   26.109513] tegradc tegradc.1: DP : Prod set failed

this message is coming from:

switch (cfg->link_bw) {
	case SOR_LINK_SPEED_G1_62:  /* RBR */
		if (!IS_ERR(dp->prod_list)) {
			err = tegra_prod_set_by_name(&dp->sor->base,
				"prod_c_rbr", dp->prod_list);
			if (err) {
				dev_warn(&dp->dc->ndev->dev, "DP : Prod set failed\n");
				return;
			}
		}
		break;
	case SOR_LINK_SPEED_G2_7:   /* HBR */
		if (!IS_ERR(dp->prod_list)) {
			err = tegra_prod_set_by_name(&dp->sor->base,
				"prod_c_hbr", dp->prod_list);
			if (err) {
				dev_warn(&dp->dc->ndev->dev, "DP : Prod set failed\n");
				return;
			}
		}
		break;
	case SOR_LINK_SPEED_G5_4:  /* HBR2 */
		if (!IS_ERR(dp->prod_list)) {
			err = tegra_prod_set_by_name(&dp->sor->base,
				"prod_c_hbr2", dp->prod_list);
			if (err) {
				dev_warn(&dp->dc->ndev->dev, "DP : Prod set failed\n");
				return;
			}
		}
		break;
	default:
		BUG();
	}

But non of the prod DT nodes exist in the nvidia supplied DT
prod_c_rbr
prod_c_hbr
prod_c_hbr2

Does anyone have DP working in R28.1? If yes, can you post you DT mods?

Thanks

K.

3

Please try to add this to prod-settings of sor. It looks missing.

prod_c_hbr {
					prod = <
						0x00000590 0x00f00000 0x00400000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ		0x04
					>;
				};
				prod_c_hbr2 {
					prod = <
						0x00000590 0x00f00000 0x00600000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ		0x06
					>;
				};
				prod_c_rbr {
					prod = <
						0x00000590 0x00f00000 0x00300000   //SOR_NV_PDISP_SOR_PLL1_0	        23:20=LOADADJ		0x03
					>;
				};
4

Hi kyler,

Have you tried the patch?
Any update?

Thanks

5

Hi,

Sorry for the delay.

Yes, I have tried the patch and the error message in longer present but I am still not able to get display port working. Am I correct in thinking that the TX1 doesn’t support a single external display port monitor connected to SOR1, I have been looking at board-panel.c and it looks like display port is only for the second display?

Many thnaks

Kyle.

6

Hi kyle.rhodes,

TX1 HW is able to output DP but currently we don’t have a official method or dtb for it.

If the error is still there, I doubt you may add it in wrong place of dtb.

[   26.109513] tegradc tegradc.1: DP : Prod set failed

Following combinations are possible for TX1 HW.

HDMI/DSI
HDMI/eDP
DP/DSI
DP/eDP

7

Hi WayneWWW,

Is the address value “0x00000590” correct? I read TX1 TRM and the address of SOR_NV_PDISP_SOR_PLL1_0 should be 0x18. So the correct address value might be 0x00000060 = 0x18 * 4. Am I right?

I followed instructions above to enable DP but failed. I faced a “link training error”.
The kernel log and modifications as attachments.
Could you give me some advise to enable DP port ?

Kernel_log.txt (138 KB)
patch.txt (51.1 KB)

8

We don’t support DP for TX1 and no plan in future.

Please refer to this thread

https://devtalk.nvidia.com/default/topic/1028642/jetson-tx1/how-to-change-hdmi-to-dp-on-r28-1/