Hi,
I have a carrier board for TX1 module that changed the HDMI to DP. The DP port is working fine with R24.2.1.
Now I have upgrade the L4T from R24.2.1 to R28.1.
I would like to know if there has any pitch updated for the DP port on R28.1 kernel code.
Hi jcc_0115,
DP is not in support scope so rel-28.1 still has no patch to enable DP but only eDP.
Hi WayneWWW,
May I know if there has schedule for support DP?
Could you advise me how to enable the DP port on R28.1?
Hi jjc_0115,
As I know this file should be added to TX1 device tree.
hardware/nvidia/platform/t210/common/kernel-dts/t210-common-platforms/tegra210-dp.dtsi
Also, dpaux status needs to set to “okay”
Hi WayneWWWW,
I have modified the DTS as you mentioned, and also hpd in the pinmux.
So far, I got the unplug/plug event when the DP re-plug, but I still got the black screen from the DP port.
hdmi_int_dp_hpd_pcc1 {
nvidia,pins = "hdmi_int_dp_hpd_pcc1";
- nvidia,function = "rsvd1";
+ nvidia,function = "dp";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
};
Attached the kernel log, Could you help me to check if there has something wrong?
dmesg.log (69 KB)
Hi,
It looks like the prod setting is not in t210 device tree. Could you try to add this under host1x/sor?
prod-settings {
prod_c_hbr {
prod = <
0x00000590 0x00f00000 0x00400000 //SOR_NV_PDISP_SOR_PLL1_0 23:20=LOADADJ 0x04
>;
};
prod_c_hbr2 {
prod = <
0x00000590 0x00f00000 0x00600000 //SOR_NV_PDISP_SOR_PLL1_0 23:20=LOADADJ 0x06
>;
};
prod_c_rbr {
prod = <
0x00000590 0x00f00000 0x00300000 //SOR_NV_PDISP_SOR_PLL1_0 23:20=LOADADJ 0x03
>;
};
};
Hi jjc_0115,
How is it going?
Hi Wanyne,
I added the prod-setting in the both of device node sor and sor1 then dump the device tree by dtc command to double check the prod-setting. But it does not work.
There is something strange about the tegra_dc_irq function in dc.c file. When I re-pluged the eDp and DP ports.
The enable_dc_irq fucntion will be called by both of tegradc.0 and tegradc.1, but tegra_dc_irq only be called by tegradc.0. Those of irq number seem to be correct. Attached the kernel log for you reference.
Do you have any suggestions on this?
sor node :
reg = <0x0 0x54540000 0x0 0x40000>;
reg-names = "sor";
compatible = "nvidia,tegra210-sor";
clock-names = "sor0", "sor_safe";
reset-names = "sor0";
nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>;
clocks = <0x41 0xb6 0x41 0xde>;
nvidia,hpd-gpio = <0x70 0xe6 0x0>;
resets = <0x41 0xb6>;
status = "okay";
nvidia,sor-audio-not-supported;
prod-settings {
#prod-cells = <0x3>;
status = "okay";
prod_c_dp {
prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
};
prod_c_hbr {
prod = <0x590 0xf00000 0x400000>;
};
prod_c_rbr {
prod = <0x590 0xf00000 0x300000>;
};
prod_c_hbr2 {
prod = <0x590 0xf00000 0x600000>;
};
};
panel-s-edp-uhdtv-15-6 {
compatible = "s-edp,uhdtv-15-6";
nvidia,is_ext_dp_panel = <0x1>;
nvidia,tx-pu-disable = <0x1>;
status = "okay";
disp-default-out {
nvidia,out-height = <0xc2>;
nvidia,out-align = <0x0>;
nvidia,out-depth = <0x18>;
nvidia,out-flags = <0x0>;
nvidia,out-order = <0x0>;
nvidia,out-width = <0x15a>;
nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
nvidia,out-type = <0x3>;
nvidia,out-xres = <0xf00>;
nvidia,out-yres = <0x870>;
nvidia,out-parent-clk = "pll_d_out0";
};
smartdimmer {
nvidia,soft-clipping-threshold = <0x80>;
nvidia,phase-in-settings = <0x0>;
nvidia,bin-width = <0xffffffff>;
nvidia,bl-device-name = "pwm-backlight";
nvidia,use-auto-pwm = <0x0>;
nvidia,aggressiveness = <0x5>;
nvidia,smooth-k-enable = <0x0>;
nvidia,phase-in-adjustments = <0x0>;
nvidia,coeff = <0x5 0x9 0x2>;
nvidia,bltf = <0x39 0x41 0x49 0x52 0x5c 0x67 0x72 0x7d 0x8a 0x96 0xa4 0xb2 0xc1 0xd0 0xe0 0xf1>;
nvidia,sd-window-enable = <0x0>;
nvidia,use-vpulse2 = <0x1>;
nvidia,smooth-k-incr = <0x40>;
nvidia,k-limit-enable = <0x1>;
nvidia,k-limit = <0xc8>;
nvidia,soft-clipping-enable = <0x1>;
status = "okay";
nvidia,use-vid-luma = <0x0>;
nvidia,hw-update-delay = <0x0>;
nvidia,blp = <0x400 0xff>;
nvidia,lut = <0xff 0xff 0xff 0xc7 0xc7 0xc7 0x99 0x99 0x99 0x74 0x74 0x74 0x55 0x55 0x55 0x3b 0x3b 0x3b 0x24 0x24 0x24 0x11 0x11 0x11 0x0 0x0 0x0>;
nvidia,fc = <0x0 0x0>;
};
display-timings {
3840x2160-32 {
nvidia,h-ref-to-sync = <0x1>;
hsync-len = <0x20>;
clock-frequency = <0x1f1e7610>;
vsync-len = <0x5>;
hfront-porch = <0x30>;
vfront-porch = <0x3>;
hback-porch = <0x50>;
nvidia,v-ref-to-sync = <0x1>;
hactive = <0xf00>;
vactive = <0x870>;
vback-porch = <0x36>;
};
};
dp-lt-settings {
lt-setting@0 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
nvidia,load-adj = <0x3>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
lt-setting@1 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
nvidia,load-adj = <0x4>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
lt-setting@2 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
nvidia,load-adj = <0x6>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
};
};
panel-s-edp-uhdtv-15-6-tonie {
compatible = "s-edp,uhdtv-15-6";
nvidia,panel-rst-gpio = <0x70 0xaa 0x0>;
nvidia,is_ext_dp_panel = <0x1>;
nvidia,panel-bl-pwm-gpio = <0x70 0xa8 0x0>;
nvidia,tx-pu-disable = <0x1>;
status = "okay";
disp-default-out {
nvidia,out-height = <0xc2>;
nvidia,out-align = <0x0>;
nvidia,out-depth = <0x18>;
nvidia,out-flags = <0x0>;
nvidia,out-order = <0x0>;
nvidia,out-width = <0x15a>;
nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
nvidia,out-type = <0x3>;
nvidia,out-xres = <0xf00>;
nvidia,out-yres = <0x870>;
nvidia,out-parent-clk = "pll_d_out0";
};
smartdimmer {
nvidia,soft-clipping-threshold = <0x80>;
nvidia,phase-in-settings = <0x0>;
nvidia,bin-width = <0xffffffff>;
nvidia,bl-device-name = "pwm-backlight";
nvidia,use-auto-pwm = <0x0>;
nvidia,aggressiveness = <0x5>;
nvidia,smooth-k-enable = <0x0>;
nvidia,phase-in-adjustments = <0x0>;
nvidia,coeff = <0x5 0x9 0x2>;
nvidia,bltf = <0x39 0x41 0x49 0x52 0x5c 0x67 0x72 0x7d 0x8a 0x96 0xa4 0xb2 0xc1 0xd0 0xe0 0xf1>;
nvidia,sd-window-enable = <0x0>;
nvidia,use-vpulse2 = <0x1>;
nvidia,smooth-k-incr = <0x40>;
nvidia,k-limit-enable = <0x1>;
nvidia,k-limit = <0xc8>;
nvidia,soft-clipping-enable = <0x1>;
status = "okay";
nvidia,use-vid-luma = <0x0>;
nvidia,hw-update-delay = <0x0>;
nvidia,blp = <0x400 0xff>;
nvidia,lut = <0xff 0xff 0xff 0xc7 0xc7 0xc7 0x99 0x99 0x99 0x74 0x74 0x74 0x55 0x55 0x55 0x3b 0x3b 0x3b 0x24 0x24 0x24 0x11 0x11 0x11 0x0 0x0 0x0>;
nvidia,fc = <0x0 0x0>;
};
display-timings {
3840x2160-32 {
nvidia,h-ref-to-sync = <0x1>;
hsync-len = <0x20>;
clock-frequency = <0x1f1e7610>;
vsync-len = <0x5>;
hfront-porch = <0x30>;
vfront-porch = <0x3>;
hback-porch = <0x50>;
nvidia,v-ref-to-sync = <0x1>;
hactive = <0xf00>;
vactive = <0x870>;
vback-porch = <0x36>;
};
};
dp-lt-settings {
lt-setting@0 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
nvidia,load-adj = <0x3>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
lt-setting@1 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
nvidia,load-adj = <0x4>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
lt-setting@2 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
nvidia,load-adj = <0x6>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
};
};
};
sor1 node
reg = <0x0 0x54580000 0x0 0x40000>;
interrupts = <0x0 0x4c 0x4>;
reg-names = "sor";
pad-names = "hdmi";
nvidia,sor1-output-type = "dp";
compatible = "dp, display";
clock-names = "sor1", "sor_safe", "sor1_brick", "sor1_src", "pll_p", "maud", "hda", "hda2codec_2x", "hda2hdmi";
reset-names = "sor1", "hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst";
nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>;
clocks = <0x41 0xb7 0x41 0xde 0x41 0x16e 0x41 0x16f 0x41 0xf3 0x41 0xca 0x41 0x7d 0x41 0x6f 0x41 0x80>;
nvidia,hpd-gpio = <0x70 0xe1 0x0>;
resets = <0x41 0xb7 0x41 0x7d 0x41 0x6f 0x41 0x80>;
status = "okay";
pad-controllers = <0x5b 0x17>;
prod-settings {
prod_list_hdmi_board = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_75m", "prod_c_hdmi_75m_150m", "prod_c_hdmi_150m_300m", "prod_c_hdmi_300m_600m";
prod_list_hdmi_soc = "prod_c_hdmi_0m_54m", "prod_c_hdmi_54m_111m", "prod_c_hdmi_111m_223m", "prod_c_hdmi_223m_300m", "prod_c_hdmi_300m_600m";
#prod-cells = <0x3>;
status = "okay";
prod {
prod = <0x3a0 0x1 0x1 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
};
prod_c_hdmi_300m_600m {
prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
board {
prod = <0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x301f00 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333e3e3e 0x148 0xffffffff 0x70707 0x170 0x40ff00 0x406600>;
};
};
prod_c_hdmi_54m_111m {
prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
};
prod_c_hdmi_223m_300m {
prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
};
prod_c_hdmi_75m_150m {
board {
prod = <0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x301300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
};
};
prod_c_hdmi_111m_223m {
prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
};
prod_c_dp {
prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
};
prod_c_54M {
prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
};
prod_c_75M {
prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
};
prod_c_hbr {
prod = <0x590 0xf00000 0x400000>;
};
prod_c_rbr {
prod = <0x590 0xf00000 0x300000>;
};
prod_c_150M {
prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xff0fe0ff 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
};
prod_c_300M {
prod = <0x3a0 0x2 0x0 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
};
prod_c_600M {
prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x0 0x170 0x40ff00 0x406600>;
};
prod_c_hbr2 {
prod = <0x590 0xf00000 0x600000>;
};
prod_c_hdmi_0m_54m {
prod = <0x3a0 0x2 0x2 0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x401380 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
board {
prod = <0x5c 0xf000700 0x1000000 0x60 0xf01f00 0x301300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x401000>;
};
};
prod_c_hdmi_54m_75m {
board {
prod = <0x5c 0xf000700 0x1000100 0x60 0xf01f00 0x301300 0x68 0xf000000 0x8000000 0x138 0xffffffff 0x333a3a3a 0x148 0xffffffff 0x0 0x170 0x40ff00 0x404000>;
};
};
prod_c_hdmi_150m_300m {
board {
prod = <0x5c 0xf000700 0x1000300 0x60 0xf01f00 0x301300 0x68 0xf000000 0xa000000 0x138 0xffffffff 0x333f3f3f 0x148 0xffffffff 0x171717 0x170 0x40ff00 0x406600>;
};
};
};
hdmi-display {
status = "disabled";
disp-default-out {
nvidia,out-xres = <0x1000>;
nvidia,out-yres = <0x870>;
};
};
dp-display {
compatible = "dp, display";
nvidia,is_ext_dp_panel = <0x1>;
nvidia,hpd-gpio = <0x70 0xe1 0x1>;
status = "okay";
disp-default-out {
nvidia,out-hotplug-state = <0x0>;
nvidia,out-align = <0x0>;
nvidia,out-flags = <0x0>;
nvidia,out-order = <0x0>;
nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
nvidia,out-type = <0x3>;
nvidia,out-parent-clk = "pll_d2_out0";
};
dp-lt-settings {
lt-setting@0 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
nvidia,load-adj = <0x3>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
lt-setting@1 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
nvidia,load-adj = <0x4>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
lt-setting@2 {
nvidia,drive-current = <0x0 0x0 0x0 0x0>;
nvidia,tx-pu = <0x0>;
nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
nvidia,load-adj = <0x6>;
nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
};
};
};
};
kernel.log (175 KB)
Hi jjc_0115,
Could you paste out the whole dts? Does sor1 has dpaux1?
Hi WayneWWW,
The dpaux and dpaux1 should be under host1x, right?
dpaux1 {
reg = <0x0 0x54040000 0x0 0x40000>;
interrupts = <0x0 0xb 0x4>;
compatible = "nvidia,tegra210-dpaux1";
clock-names = "dpaux1", "pll_dp";
reset-names = "dpaux1";
clocks = <0x41 0xcf 0x41 0x12f>;
resets = <0x41 0xcf>;
status = "okay";
prod-settings {
#prod-cells = <0x3>;
prod_c_dpaux_dp {
prod = <0x124 0x37fe 0x24c2>;
};
prod_c_dpaux_hdmi {
prod = <0x124 0x700 0x400>;
};
};
};
r28_dts.log (1020 KB)
Any output from tegra_dp_irq_evt_worker? Could you upload the dmesg with only tegradc1->SOR1(DP)?
Let’s isolate eDP here.
Hi WayneWWW,
Here is the only enabled dc1 kernel log.
tegradc1.log (97.9 KB)
Are you sure all the hardware connection and signal is correct as rel-24.2.1?
Can you check why dc still selects eDP driver for you?
Hi WayneWWW,
You are right, The display output from the eDP port, I need sometimes to investigate on it.
Btw, How did you know the dc selects eDP?
jjc_0115,
Because your debug message reveal it. In tegra_primary_panel_get_dt_node(), could you check why it didn’t return in the first “dp-display” check?
[ 0.521126] Tonie's Msg : internal_panel_select_by_disp_board_id dc_out->type:3 !
[ 0.521153] Tonie's Msg : internal_panel_select_by_disp_board_id is_edp_s_2160p_15_6 !
I think it is due to your if(np_sor) does not pass.
DC OR NODE connected to /host1x/sor1 but not /host1x/sor.
if (pdata && !strcmp(pdata->dc_or_node_name, "/host1x/sor"))
np_sor = of_find_node_by_path(SOR_NODE);
Hi,
How is the porting? Is it working now?
Hi, WayneWWW,
I am also working on this issue but failed.
I can make DP and eDP executing both but still cannot see the output.
I force eDP on /host1x/sor and DP on /host1x/sor1.
And I also check those lt-settings are independent between these two ports.
In terms of eDP, dp lt has passed.
In terms of DP, it failed on
dp lt: CE retry limit 5 reached
And then the system seems ‘slow down’…
The log message shows very slow…
The last error messages are :
[ 10.647483] sched: RT throttling activated
[ 10.647523] Host read timeout at address 5454006c
[ 10.647669] tegradc tegradc.0: sor_poll_register 0x33: timeout
Could you please advise?
Hi Tonie,
Do you co-work with jjc_0115? Why does your name appear in jjc_0115’s log? A coincidence?
What is your current status? Any dmesg?