Hi, I seems enable all but still cannot see the output.
Here are the log :
[ 3.746347] tegradc tegradc.0: nominal-pclk:25200000 parent:25200000 div:1.0 pclk:25200000 24948000~27468000
[ 3.768702] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 1
[ 3.772292] dp lt: switching from state 0 (Reset) to state 0 (Reset)
[ 3.778655] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[ 3.785230] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 3.791275] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[ 3.797795] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 3.804360] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 3.811133] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 3.817893] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 3.825616] dp lt: CR not done
[ 3.828185] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 3.834776] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 3.841899] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 3.849001] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 3.856108] dp lt: CR retry
[ 3.858866] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 3.866774] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[ 3.873085] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 3.879859] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 3.886617] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 3.893364] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 3.901108] dp lt: CR not done
[ 3.903670] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 3.910278] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 3.917383] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 3.924475] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 3.931591] dp lt: CR retry
[ 3.934352] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 3.942262] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[ 3.948585] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 3.955345] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 3.962091] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 3.968863] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 3.976767] dp lt: CR done
[ 3.978293] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 3.986724] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[ 3.994761] dp lt: CE not done
[ 3.997116] dp lt: new config: lane 0: vs level: 2, pe level: 1, pc2 level: 0
[ 4.003689] dp lt: new config: lane 1: vs level: 2, pe level: 1, pc2 level: 0
[ 4.010813] dp lt: new config: lane 2: vs level: 2, pe level: 1, pc2 level: 0
[ 4.017920] dp lt: new config: lane 3: vs level: 2, pe level: 1, pc2 level: 0
[ 4.025031] dp lt: config: lane 0: vs level: 2, pe level: 1, pc2 level: 0
[ 4.031772] dp lt: config: lane 1: vs level: 2, pe level: 1, pc2 level: 0
[ 4.038545] dp lt: config: lane 2: vs level: 2, pe level: 1, pc2 level: 0
[ 4.045304] dp lt: config: lane 3: vs level: 2, pe level: 1, pc2 level: 0
[ 4.052644] dp lt: CE retry
[ 4.054820] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization)
[ 4.063775] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[ 4.072307] dp lt: CE done
[ 4.073309] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 4.082094] dp_audio switch 1
[ 4.085239] tegradc tegradc.0: probed
[ 4.088741] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[ 4.195022] Console: switching to colour frame buffer device 480x135
[ 4.290440] tegradc tegradc.0: fb registered
[ 4.774091] tegradc tegradc.0: dp: plug event received
Please advise…