Enable eDP on tegradc.0 with SOR

Hi, I am trying to enable eDP on tegradc.0 with SOR.
Here are the list of what I had enabled :

ubuntu@tegra-ubuntu:/sys/devices/platform/host1x$ ls
54540000.sor capabilities isp.1 nvjpg tegradc.0 uevent
54580000.sor1 driver modalias power tegradc.1 vi
546c0000.i2c gpu.0 msenc subsystem tsec vi-bypass.28
acm isp.0 nvdec syncpt tsecb vic03
ubuntu@tegra-ubuntu:/sys/devices/platform/host1x$

And I still cannot get display from ‘DP0’.

Is there any suggestion/information can provide ?

Thanks.

Tonie

Here are the log

[ 0.567836] platform tegradc.0: domain=ffffffc0ff114458 allocates as[0]=ffffffc0ff198248
[ 0.577939] platform tegradc.0: IOVA linear map 0x00000000f6200000(4800000)
[ 0.586890] platform tegradc.0: IOVA linear map 0x00000000faa00000(4800000)
[ 0.592234] platform tegradc.0: IOVA linear map 0x00000000df400000(16c00000)
[ 0.599363] platform tegradc.1: domain=ffffffc0ff1142d8 allocates as[0]=ffffffc0ff1982b0
[ 0.610950] platform tegradc.1: IOVA linear map 0x00000000f6200000(4800000)
[ 0.619892] platform tegradc.1: IOVA linear map 0x00000000faa00000(4800000)
[ 0.625232] platform tegradc.1: IOVA linear map 0x00000000df400000(16c00000)
[ 3.206146] tegradc tegradc.0: Display dc.54200000 registered with id=0
3.419424] tegradc tegradc.0: DT parsed successfully 20
[ 3.424808] tegradc tegradc.0: DT parsed successfully
[ 3.462994] tegradc tegradc.0: Error: out->type:3 out_ops->init() failed
[ 3.469703] tegradc tegradc.0: failed to initialize DC out ops
[ 3.475579] tegradc: probe of tegradc.0 failed with error -22

Hi, I seems enable all but still cannot see the output.

Here are the log :

[ 3.746347] tegradc tegradc.0: nominal-pclk:25200000 parent:25200000 div:1.0 pclk:25200000 24948000~27468000
[ 3.768702] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 1
[ 3.772292] dp lt: switching from state 0 (Reset) to state 0 (Reset)
[ 3.778655] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[ 3.785230] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 3.791275] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[ 3.797795] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 3.804360] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 3.811133] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 3.817893] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 3.825616] dp lt: CR not done
[ 3.828185] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 3.834776] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 3.841899] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 3.849001] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 3.856108] dp lt: CR retry
[ 3.858866] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 3.866774] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[ 3.873085] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 3.879859] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 3.886617] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 3.893364] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 3.901108] dp lt: CR not done
[ 3.903670] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 3.910278] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 3.917383] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 3.924475] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 3.931591] dp lt: CR retry
[ 3.934352] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 3.942262] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[ 3.948585] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 3.955345] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 3.962091] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 3.968863] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 3.976767] dp lt: CR done
[ 3.978293] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 3.986724] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[ 3.994761] dp lt: CE not done
[ 3.997116] dp lt: new config: lane 0: vs level: 2, pe level: 1, pc2 level: 0
[ 4.003689] dp lt: new config: lane 1: vs level: 2, pe level: 1, pc2 level: 0
[ 4.010813] dp lt: new config: lane 2: vs level: 2, pe level: 1, pc2 level: 0
[ 4.017920] dp lt: new config: lane 3: vs level: 2, pe level: 1, pc2 level: 0
[ 4.025031] dp lt: config: lane 0: vs level: 2, pe level: 1, pc2 level: 0
[ 4.031772] dp lt: config: lane 1: vs level: 2, pe level: 1, pc2 level: 0
[ 4.038545] dp lt: config: lane 2: vs level: 2, pe level: 1, pc2 level: 0
[ 4.045304] dp lt: config: lane 3: vs level: 2, pe level: 1, pc2 level: 0
[ 4.052644] dp lt: CE retry
[ 4.054820] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization)
[ 4.063775] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[ 4.072307] dp lt: CE done
[ 4.073309] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 4.082094] dp_audio switch 1
[ 4.085239] tegradc tegradc.0: probed
[ 4.088741] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[ 4.195022] Console: switching to colour frame buffer device 480x135
[ 4.290440] tegradc tegradc.0: fb registered
[ 4.774091] tegradc tegradc.0: dp: plug event received

Please advise…

Hi,

Is there any NV people can help ?

Hi

How did you activate the SOR?

Thank you for your patience, we are currently investigating this issue.

I have the same error:
7.582964] tegradc tegradc.0: Display dc.54200000 registered with id=0
[ 7.635119] tegradc tegradc.0: DT parsed successfully
[ 7.640320] tegradc tegradc.0: Error: out->type:3 out_ops->init() failed
[ 7.646720] tegradc tegradc.0: failed to initialize DC out ops
[ 7.652635] tegradc: probe of tegradc.0 failed with error -22

How is the status of this issue?

Hi su,

Could you take a look at your tegra_dc_dp_init in dp.c to see which part does not pass?

Hello all

How to Enable eDP on tegradc.0 in the kernel source V24.1 ?

Could any NV people provide the normal step to Enable eDP on tegradc.0 ??

Hi etta,

We support AUO 14" 1080p eDP panel on v24.1 and v24.2

The steps to enable this display:

  1. We will be using p2371-2180.conf for this, with relevant changes

  2. Edit p2371-2180.conf and update DTB-FILE parameter with AUO DTB name
    tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb

  3. Change the extlinux.config. file with correct DTB, like blow
    FDT /boot/<tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb>

  4. flash with p2371-2180


To add your own display, you need to write your own dts.

dts needed for AUO 14" eDP
arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
arch/arm64/boot/dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts
files related
arch/arm/mach-tegra/board-panel.c
arch/arm/mach-tegra/panel-a-edp-1080p-14-0.c

Hi WayneWWW

Thanks your information , i have some progressed in my study.

I followed your step to enable eDP to develop my project.
But i have some error and some confuse need to help.

here is my test step :

  1. I buy a DP to HDMI converter, i design a convert board to connect the J23 eDP pin and DP to HDMI converter. So it can connect HDMI monitor.

  2. change extlinux.conf from tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb to tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb

  3. use V24.1 tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb to update in /boot

  4. reboot

But it can’t work and have error message as below:
[ 13.935541] avdd_lcd regulator get failed
[ 13.935542] dsi regulator get failed
[ 15.716524] avdd_lcd regulator get failed
[ 15.716525] dsi regulator get failed

Q1 How do i fix this problem??
Q2 Did eDP pin can be the external displays on TX1??

If eDP pin can’t be external displays i need to buy AUO panel and change my project.
please give me some suggestion.

hi,

I am not sure if there is a missing regulator on v24.1 because I verified it on v24.2. There are some kernel changes. Could you try it on v24.2??

Dear WayneWWW

I use jetpack2.3 to flash the device and build V24.2 kernel.
but it have no output from eDP.
here is display message

[ 2.284627] lp855x 1-002c: failed to read 0x00
[ 2.288964] lp855x 1-002c: pre init device err: -121
[ 2.293914] lp855x 1-002c: device config err: -121
[ 2.298677] lp855x: probe of 1-002c failed with error -121
[ 2.304549] pwm-backlight pwm-backlight: PWM request fail by devm_pwm_get, trying of_pwm_get
[ 2.313785] tsec tsec: initialized
[ 2.316924] tsec tsecb: initialized
[ 2.321149] nvdec nvdec: initialized
[ 2.325454] falcon vic03: initialized
[ 2.328418] falcon msenc: initialized
[ 2.331819] falcon nvjpg: initialized
[ 2.335265] tegradc tegradc.0: Display dc.54200000 registered with id=0
[ 2.341010] of_dc_parse_platform_data: No dc-or-node is defined in DT
[ 2.347522] display board info: id 0x0, fab 0x0
[ 2.352527] display board info: id 0x0, fab 0x0
[ 2.356846] of_dc_parse_platform_data: could not find vrr-settings node
[ 2.363023] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[ 2.369609] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[ 2.376605] tegradc tegradc.0: DT parsed successfully
[ 2.381906] tegradc tegradc.0: DSI: HS clock rate is 467500
[ 2.387828] avdd_lcd regulator get failed
[ 2.391097] dsi regulator get failed
[ 2.395540] tegradc tegradc.0: nominal-pclk:155774000 parent:155773829 div:1.0 pclk:155773829 154216260~169793660
[ 2.469266] tegradc tegradc.0: probed
[ 2.539871] tegradc tegradc.0: nominal-pclk:155666000 parent:466996875 div:3.0 pclk:155665625 154109340~169675940
[ 2.557929] Console: switching to colour frame buffer device 150x120
[ 2.590248] tegradc tegradc.0: fb registered
[ 2.594616] tegradc tegradc.1: Display dc.54240000 registered with id=1
[ 2.601042] of_dc_parse_platform_data: No dc-or-node is defined in DT
[ 2.607636] parse_tmds_config: No tmds-config node
[ 2.612323] of_dc_parse_platform_data: could not find vrr-settings node
[ 2.618790] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[ 2.625389] of_dc_parse_platform_data: could not find SD settings node
[ 2.631882] of_dc_parse_platform_data: could not find cmu node
[ 2.637678] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[ 2.644636] tegradc tegradc.1: DT parsed successfully
[ 2.649895] hdmi: couldn’t get regulator vdd_hdmi_5v0
[ 2.655093] gpio wake53 for gpio=225
[ 2.659045] tegradc tegradc.1: probed
[ 2.730969] tegradc tegradc.1: fb registered

and the console will show
[ 17.990045] avdd_lcd regulator get failed
[ 17.990047] dsi regulator get failed

I want the dual output screen not use Embedded panel to output so i only connect J23 eDP pin and DP to HDMI converter.

The TX1 can support two external displays or not ?
should i disable dsi and lcd function to achieve the my feature?
Do you have DTS document to help to study TX1 DTS ??

hi WayneWWW

tx1 reboot -> change eDp resolution OK…but

This procedure is performed with power on.

edid change(1920x1080 3840x2160 …) -> link training ok -> xrandr and fbset -> change fail

How do you do change eDp resolution?

I tried and tried, but did not succeed.

I am eager to have your help.

There is a thread discussing about dual monitor.
https://devtalk.nvidia.com/default/topic/951911/question-dual-monitor/
Also, we have Tegra Linux Driver Package Development Guide for device tree, but the example in that document is for sensor driver.
http://developer.nvidia.com/embedded/dlc/l4t-documentation-24-1

For panel,dtsi file path: kernel/arch/arm/boot/dts/panel-*.dtsi
Docs: kernel/Documentation/devicetree/bindings/video/nvidia,tegra-dp.txt (tegra210 for your case)

Hi ChiHong,

Do you mean modifying the edid data in EEPROM and then reboot??

Could you provide the method that I can reproduce this problem on my devices?

WayneWWW, I think I’m seeing the same thing as ChiHong has reported.

I managed to get eDP0 working on TX1. The eDP0 output goes through a DP-to-HDMI converter to a HDMI display. At kernel boot time, the tegra dp driver would check EDID (EEPROM of the HDMI display) to determine its output video resolution. That is, when I hook it up to different HDMI displays, the HDMI output would be either 1080p60 or 720p60 depending on EDID.

However, the problem is that after the system is up and running I cannot manually change eDP0 resolution. It would be stuck at the resolution determined during driver initialization time.

Could you help to check if it’s possible to change eDP0 resolution on the fly? Thanks.

Hi jkjung13,

Because eDP does not support hpd in our internal use, it won’t read edid again after you change monitor through HDMI hot plug.

You may need to modify the driver code.

Hi WayneWWW,

Can you provide schematic of E1824 display board.?

If i want to use AUO 10.1" or 11.6" panel what modification i need to in driver or dtsi file?
http://www.auo.com/?sn=149&lang=en-US&c=34&n=364
http://www.auo.com/?sn=149&lang=en-US&c=34&n=336

Does AUO 14" eDP panel comes with touch also?
And if yes how to enable touch from the kernel.?
If no, can you recommend any other touch screen working with TX1.

Hi RiteshPanchal,

Please reference to the TX1 OEM design guide for further detail of the .

Do you have the spec of each panel? I only see simple profile in your link.