How to make a kernel with Dual-Diplay on R28.1

We are trying to make a system to use 2 displays on L4T R28.1,
but now we have not yet finish it.

In this thread, you said:
What is the number of display connector?
https://devtalk.nvidia.com/default/topic/982333/jetson-tx1/what-is-the-number-of-display-connector-/
> Yes, for TX1/2 HDMI+ DSI/eDP could work at same time. Please refer to sw feature of TX1/2.

We made a baseboard in which eDP signals are connected external Display Port connector.
The previous versions are well operating.

[L4T R23.1]

  • When the TX1 module with L4T is moved from these product to our baseboard,
    the dual-display behaves well too.

[L4T R24.2.1]

  • A reference implementation by RYOYO Electro (Japan Reseller)
  • To install the L4T from JetPack, and patch it from RYOYO’s support.

We have to use the newest MultimediaAPI, then we want to make the dual-display environment on R28.1.

I’ll explain according to procedures, below.
If it is something wrong, please point out the error(s).

(1) Install L4T from JetPack 3.1
—> directory is /home/ubuntu/work/

(2) Download and extract the kernel source package (https://developer.nvidia.com/embedded/dlc/l4t-sources-28-1)
—> directory is /home/ubuntu/work/modify28.1/

(3) Download and extract the GCC tool chain (https://developer.nvidia.com/embedded/dlc/l4t-gcc-toolchain-64-bit-28-1)
—> directory is /home/ubuntu/work/gcc64

(4) Patch the device tree source files.

(5) Build DTB file

~/work/modify28.1/kernel/kernel-4.4$ make O=~/work/modify28.1/out CROSS_COMPILE=~/work/gcc64/install/bin/aarch64-unknown-linux-gnu- ARCH=arm64 dtbs

(6) Overwrite the modified DTB file to the install tree

cp ~/work/modify28.1/out/arch/arm64/boot/dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb ~/work/64_TX1/Linux_for_Tegra_64_tx1/kernel/dtb/

(7) Set TX1 to the RECOVERY mode (Connect to host PC by USB)

(8) Flash the DTB partition

~/work/64_TX1/Linux_for_Tegra_64_tx1/$ sudo ./flash.sh -r -k DTB jetson-tx1 mmcblk0p1

(9) Connect 2 Display (Display Port and HDMI) to TX1 (our baseboard)

(10) Reboot TX1

Then the kernel becomes hung-up or slow-down.

The patch is:

diff -uprN base28.1/hardware/nvidia/platform/t210/common/kernel-dts/t210-common-platforms/tegra210-dp.dtsi modify28.1/hardware/nvidia/platform/t210/common/kernel-dts/t210-common-platforms/tegra210-dp.dtsi
--- base28.1/hardware/nvidia/platform/t210/common/kernel-dts/t210-common-platforms/tegra210-dp.dtsi	2017-07-20 16:36:24.000000000 +0900
+++ modify28.1/hardware/nvidia/platform/t210/common/kernel-dts/t210-common-platforms/tegra210-dp.dtsi	2017-08-28 10:09:50.501572493 +0900
@@ -36,7 +36,7 @@
 							   TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
 							   TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
 							   TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
-					nvidia,out-parent-clk = "pll_d";
+					nvidia,out-parent-clk = "pll_d2_out0";
 				};
 				dp-lt-settings {
 					lt-setting@0 {
diff -uprN base28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/jetson-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi modify28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/jetson-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi
--- base28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/jetson-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi	2017-07-20 16:36:24.000000000 +0900
+++ modify28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/jetson-platforms/tegra210-jetson-cv-power-tree-p2597-2180-a00.dtsi	2017-08-25 15:00:28.852547109 +0900
@@ -318,6 +318,10 @@
 			/* eDP */
 			vdd_ds_1v8-supply  = <&en_dvdd_disp_1v8>;
 			avdd_io_edp-supply = <&max77620_gpio7>;
+			vdd-dp-pwr-supply = <&vdd_3v3>;
+			avdd-dp-pll-supply = <&max77620_sd3>;
+			vdd-edp-sec-mode-supply = <&max77620_gpio7>;
+			vdd-dp-pad-supply = <&en_dvdd_disp_1v8>;
 		};
 
 		vi {
diff -uprN base28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts modify28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
--- base28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts	2017-07-20 16:36:24.000000000 +0900
+++ modify28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts	2017-08-25 14:53:29.456559208 +0900
@@ -30,6 +30,7 @@
 #include <panels/panel-a-wuxga-8-0.dtsi>
 #include <panels/panel-s-edp-uhdtv-15-6.dtsi>
 #include <t210-common-platforms/tegra210-ers-hdmi-e2190-1100-a00.dtsi>
+#include <t210-common-platforms/tegra210-dp.dtsi>
 #include <tegra210-soc/tegra210-sdhci.dtsi>
 #include "jetson-platforms/tegra210-p2180-common.dtsi"
 #include "jetson-platforms/tegra210-thermal-fan-est-p2530-0930.dtsi"
@@ -241,9 +242,10 @@
 			status = "okay";
 			nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
 			nvidia,emc-clk-rate = <300000000>;
+			nvidia,cmu-enable = <1>;
 			nvidia,fb-bpp = <32>; /* bits per pixel */
 			nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
-			nvidia,dc-or-node = "/host1x/dsi";
+			nvidia,dc-or-node = "/host1x/sor";
 		};
 
 		/* tegradc.1 */
@@ -279,6 +281,7 @@
 			};
 			panel-s-edp-uhdtv-15-6 {
 				status = "okay";
+				nvidia,is_ext_dp_panel = <1>;
 				nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0>; /* PV0 */
 				nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 2) 0>; /* PV2 */
 				smartdimmer {
@@ -287,6 +290,9 @@
 			};
 		};
 
+		dpaux {
+			status = "okay";
+		};
 		dpaux1 {
 			status = "okay";
 		};
diff -uprN base28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts modify28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts
--- base28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts	2017-07-20 16:36:24.000000000 +0900
+++ modify28.1/hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts	2017-08-25 15:03:19.600542183 +0900
@@ -32,7 +32,7 @@
 
 	host1x {
 		dc@54200000 {
-			status = "disabled";
+			status = "okay";
 		};
 
 		dsi {
@@ -53,6 +53,10 @@
 				status = "disabled";
 			};
 		};
+
+		dpaux1 {
+			status = "okay";
+		};
 	};
 
 	i2c@7000c400 {

Attatched log files are with each clock setting (disp1 parent clock):

  • 1: clk_m
  • 2: pll_p
  • 3: pll_d_out0
  • 4: pll_d2_out0

20170830_DualDisplayLog.zip (122 KB)

Hi mynaemi,

I am checking this internally. Sorry for your inconvenience.

Dear WayneWWW,

Thanks very very much!
Because of changed structure of “Device Tree”,
we are confused to make a dual-display environment.

We are looking forward your suggestion.

Best Regards,

Hi mynaemi,

Sorry for the late reply.

Could you share the boot up log? which should have some error messages.

Dear WayneWWW,

I will post on behalf of miynaemi.
I will attach the boot log.

Best Regards,
4-hung-pll_d2_out0.log (212 KB)

Hi mtakahas,

This is my patch for bringing up AUO-eDP panel on my device. Sorry that I don’t have enough time for this, still have some issues (backlight, pclk) with this patch, but link training works good on my side. I can see EDID in tegra.

be0874c.diff.zip (1.64 KB)

Hi mynaemi,

How is your bring up? Is it okay?

Hi WayneWWW,

Thanks a lot for your support.

Today, we (mtakahas) tried to build it with your patch,
but it was not normaly operating.

Below, The summary of boot log about “tegradc.0”

DTS File Name: /home/ubuntu/work3/modify28.1/kernel/kernel-4.4/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
DTB Build time: Sep 26 2017 14:25:05

DTS File Name: /home/ubuntu/work3/modify28.1/kernel/kernel-4.4/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
DTB Build time: Sep 26 2017 14:25:05

display board info: id 0xffff, fab 0x0
display board info: id 0xffff, fab 0x0
parse_dp_settings: No lt-data node. Using default setting.
tegradc tegradc.0: DT parsed successfully
tegradc tegradc.0: Display dc.ffffff8000980000 registered with id=0
display board info: id 0xffff, fab 0x0

tegradc tegradc.0: probed

tegradc tegradc.0: fb registered

tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
tegradc tegradc.0: pclk out of range!
tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed

tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
DC OR NODE connected to /host1x/sor1
tegradc tegradc.1: DT parsed successfully
tegradc tegradc.1: Display dc.ffffff8007400000 registered with id=1
tegra-i2c 7000c700.i2c: no acknowledge from address 0x50
tegradc tegradc.1: probed


tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
tegradc tegradc.0: pclk out of range!
tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed
tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
tegradc tegradc.0: pclk out of range!
tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed

tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed

tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
tegradc tegradc.0: pclk out of range!
tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed

tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
tegradc tegradc.0: pclk out of range!
tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed
tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed

Hi mynaemi,

I am sorry that this issue also happens on my device. Please try to modify the tegra_dc_vga_mode in dc.c to this mode and try again.

+struct fb_videomode tegra_dc_720p_mode = {
+       .refresh = 59,
+       .xres = 720,
+       .yres = 480,
+       .pixclock = KHZ2PICOS(37037),
+       .hsync_len = 62,        /* h_sync_width */
+       .vsync_len = 6,         /* v_sync_width */
+       .left_margin = 60,      /* h_back_porch */
+       .upper_margin = 30,     /* v_back_porch */
+       .right_margin = 16,     /* h_front_porch */
+       .lower_margin = 9,      /* v_front_porch */
+       .vmode = FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA,
+       .sync = 0,
+};

Hi WayneWWW,

Thanks your reply.

Which file is the “dc.c” ?
~/kernel/kernel-4.4/drivers/gpu/drm/tegra/dc.c ?
~/kernel/display/drivers/video/tegra/dc/dc.c ?
Not the former, is it the latter ?

Yes, ~/kernel/display/drivers/video/tegra/dc/dc.c is the correct display controller file for tegra. The other is a legacy one.

Hi WayneWWW,

We have tried to make it with your 2 patches.

  • for dts files (be0874c.diff.zip)
  • for dc.c file

(1) To edit dts and dc.c

(2) To build a kernel

ubuntu@hostpc:~/work3/modify28.1/kernel/kernel-4.4$ make CROSS_COMPILE=~/work3/install/bin/aarch64-unknown-linux-gnu- ARCH=arm64 mrproper
ubuntu@hostpc:~/work3/modify28.1/kernel/kernel-4.4$ make O=~/work3/modify28.1/out CROSS_COMPILE=~/work3/install/bin/aarch64-unknown-linux-gnu- ARCH=arm64 tegra21_defconfig
ubuntu@hostpc:~/work3/modify28.1/kernel/kernel-4.4$ make O=~/work3/modify28.1/out CROSS_COMPILE=~/work3/install/bin/aarch64-unknown-linux-gnu- ARCH=arm64 Image

(3) To build a dtb file

ubuntu@hostpc:~/work3/modify28.1/kernel/kernel-4.4$ make O=~/work3/modify28.1/out CROSS_COMPILE=~/work3/install/bin/aarch64-unknown-linux-gnu- ARCH=arm64 dtbs

(4) To modify a boot-image
(a) To overwrite DTB section

ubuntu@hostpc:~/work3/$ cp ~/work3/modify28.1/out/arch/arm64/boot/dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb ~/work3/64_TX1/Linux_for_Tegra_64_tx1/kernel/dtb/tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb
ubuntu@hostpc:~/work3/64_TX1/Linux_for_Tegra_64_tx1/$ sudo ./flash.sh -r -k DTB jetson-tx1 mmcblk0p1

(b) To edit FDT section in /boot/extlinux/extlinux.conf

In (4)-(a), the display connected via DisplayPort does not receive any signal and is black-out.
In (4)-(b), Jetson TX1 is hung-up in the booting sequence.

The Boot-Logs are attached, and the summaries are below:

(4)-(a)

U-Boot 2016.07-g0ce7ca2 (Jul 20 2017 - 00:37:03 -0700)

TEGRA210
Model: NVIDIA P2371-2180
Board: NVIDIA P2371-2180

p2371-2180 eMMC boot options
1:	primary kernel
2:	debug kernel
Enter choice: 1:	primary kernel
Retrieving file: /boot/initrd
0 bytes read in 64 ms (0 Bytes/s)
Retrieving file: /boot/Image
20984368 bytes read in 527 ms (38 MiB/s)
append: root=/dev/mmcblk0p1 rw rootwait console=ttyS0,115200n8 console=tty0 OS=l4t fbcon=map:0 net.ifnames=0 androidboot.modem=none androidboot.serialno=03245162101650c08305 androidboot.security=non-secure tegraid=21.1.2.0.0 ddr_die=2048M@2048M ddr_die=2048M@4096M section=256M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 debug_uartport=lsport,0 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff2bf000 nvdumper_reserved=0xff23f000 core_edp_mv=1125 core_edp_ma=4000 gpt android.kerneltype=normal androidboot.touch_vendor_id=0 androidboot.touch_panel_id=63 androidboot.touch_feature=0 androidboot.bootloader=00.00.2014.50-t210-fadd1be5 androidboot.verifiedbootstate=orange root=/dev/mmcblk0p1 rw rootwait

Starting kernel ...

[    0.233518] platform tegradc.0: domain=ffffffc0fa238918 allocates as[0]=ffffffc0fa1442b0
[    0.234145] platform tegradc.0: IOVA linear map 0x00000000c6000000(2a000000)
[    0.234548] platform tegradc.1: domain=ffffffc0fa238c18 allocates as[0]=ffffffc0fa144318
[    0.235174] platform tegradc.1: IOVA linear map 0x00000000c6000000(2a000000)

[    0.526395] DC OR NODE connected to /host1x/sor
[    0.526508] display board info: id 0xffff, fab 0x0
[    0.526623] display board info: id 0xffff, fab 0x0
[    0.526733] parse_dp_settings: No lt-data node. Using default setting.
[    0.526935] tegradc tegradc.0: DT parsed successfully
[    0.526998] tegradc tegradc.0: Display dc.ffffff8000980000 registered with id=0

[    0.529172] tegradc tegradc.0: probed

[    2.698781] tegradc tegradc.0: fb registered

[    2.945073] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[    2.945079] tegradc tegradc.0: pclk out of range!
[    2.945086] tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed

[    3.482734] tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
[    3.483110] DC OR NODE connected to /host1x/sor1
[    3.483360] tegradc tegradc.1: DT parsed successfully
[    3.483407] tegradc tegradc.1: Display dc.ffffff8007400000 registered with id=1
[    3.486417] tegra-i2c 7000c700.i2c: no acknowledge from address 0x50
[    3.487699] tegradc tegradc.1: probed

[    4.740749] tegradc tegradc.1: fb registered

Ubuntu 16.04 LTS tegra-ubuntu ttyS0

nvidia@tegra-ubuntu:~$

[    8.617040] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[    8.617044] tegradc tegradc.0: pclk out of range!
[    8.617046] tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed
[    9.155328] tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
[    9.455897] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[    9.455926] tegradc tegradc.0: pclk out of range!
[    9.455952] tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed
[    9.561698] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[    9.659418] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[    9.995353] tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed

[   13.073133] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[   13.073137] tegradc tegradc.0: pclk out of range!
[   13.073140] tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed
[   13.610818] tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
[   13.941127] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[   13.941130] tegradc tegradc.0: pclk out of range!
[   13.941133] tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed
[   14.479378] tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed

nvidia@tegra-ubuntu:~$

(4)-(b)

U-Boot 2016.07-g0ce7ca2 (Jul 20 2017 - 00:37:03 -0700)

TEGRA210
Model: NVIDIA P2371-2180
Board: NVIDIA P2371-2180

p2371-2180 eMMC boot options
1:	primary kernel
2:	debug kernel
Enter choice: 2
2:	debug kernel
Retrieving file: /boot/initrd
0 bytes read in 64 ms (0 Bytes/s)
Retrieving file: /boot/Image
20984368 bytes read in 527 ms (38 MiB/s)
append: root=/dev/mmcblk0p1 rw rootwait console=ttyS0,115200n8 console=tty0 OS=l4t fbcon=map:0 net.ifnames=0 androidboot.modem=none androidboot.serialno=03245162101650c08305 androidboot.security=non-secure tegraid=21.1.2.0.0 ddr_die=2048M@2048M ddr_die=2048M@4096M section=256M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 debug_uartport=lsport,0 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff2bf000 nvdumper_reserved=0xff23f000 core_edp_mv=1125 core_edp_ma=4000 gpt android.kerneltype=normal androidboot.touch_vendor_id=0 androidboot.touch_panel_id=63 androidboot.touch_feature=0 androidboot.bootloader=00.00.2014.50-t210-fadd1be5 androidboot.verifiedbootstate=orange root=/dev/mmcblk0p1 rw rootwait
Retrieving file: /boot/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp_20171003.dtb
444167 bytes read in 92 ms (4.6 MiB/s)

Starting kernel ...

[    0.213251] platform 70016000.bpmp: domain=ffffffc0fa139918 allocates as[0]=ffffffc0fa14c178
[    0.213788] bpmp: ping status is 0
[    0.213888] bpmp 70016000.bpmp: firmware tag is \FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF\FF
[    0.214143] bpmp 70016000.bpmp: probe ok
[    0.214792] mc: mapped MMIO address: 0xffffff800007e000 -> 0x70019000
[    0.214895] mc: mapped MMIO address: 0xffffff80000b6000 -> 0x7001c000
[    0.214990] mc: mapped MMIO address: 0xffffff80000dc000 -> 0x7001d000
[    0.215079] mc-err: Set intmask: 0x23d40
[    0.215279] smmu_dump_pagetable(): fault_address=0x00000000ff2c0090 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[    0.215325] mc-err: (1) csr_avpcarm7r: EMEM decode error on PDE or PTE entry
[    0.215352] mc-err:   status = 0x6000200f; addr = 0xff2c0090
[    0.215377] mc-err:   secure: no, access-type: read, SMMU fault: nr-nw-s
[    0.215431] smmu_dump_pagetable(): fault_address=0x00000000ff2c0090 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[    0.215468] mc-err: (1) csr_avpcarm7r: EMEM decode error on PDE or PTE entry
[    0.215492] mc-err:   status = 0x6000200f; addr = 0xff2c0090
[    0.215516] mc-err:   secure: no, access-type: read, SMMU fault: nr-nw-s
[    0.215577] smmu_dump_pagetable(): fault_address=0x00000000ff2c0090 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[    0.215615] mc-err: (1) csr_avpcarm7r: EMEM decode error on PDE or PTE entry
[    0.215640] mc-err:   status = 0x6000200f; addr = 0xff2c0090
[    0.215664] mc-err:   secure: no, access-type: read, SMMU fault: nr-nw-s
[    0.215714] smmu_dump_pagetable(): fault_address=0x00000000ff2c0090 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[    0.215751] mc-err: (1) csr_avpcarm7r: EMEM decode error on PDE or PTE entry
[    0.215775] mc-err:   status = 0x6000200f; addr = 0xff2c0090
[    0.215798] mc-err:   secure: no, access-type: read, SMMU fault: nr-nw-s
[    0.215839] mc-err: Too many MC errors; throttling prints

[    0.233679] platform tegradc.0: domain=ffffffc0fa245918 allocates as[0]=ffffffc0fa14c2b0
[    0.234305] platform tegradc.0: IOVA linear map 0x00000000c6000000(2a000000)
[    0.234710] platform tegradc.1: domain=ffffffc0fa245c18 allocates as[0]=ffffffc0fa14c318
[    0.235340] platform tegradc.1: IOVA linear map 0x00000000c6000000(2a000000)

[    0.526846] DC OR NODE connected to /host1x/sor
[    0.526950] Node path /chosen/display-board not found
[    0.526972] display board info: id 0x0, fab 0x0
[    0.527085] display board info: id 0x0, fab 0x0
[    0.527165] parse_dp_settings: No lt-data node. Using default setting.
[    0.527334] tegradc tegradc.0: DT parsed successfully
[    0.527390] tegradc tegradc.0: Display dc.ffffff8000980000 registered with id=0
[    0.527721] display board info: id 0x0, fab 0x0
[    0.529510] tegradc tegradc.0: probed

[    2.986375] tegradc tegradc.0: fb registered

[    3.229143] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[    3.229149] tegradc tegradc.0: pclk out of range!
[    3.229155] tegradc tegradc.0: tegra_dc_init: tegra_dc_program_mode failed

[    3.770811] tegradc tegradc.0: _tegra_dc_controller_enable: tegra_dc_init failed
[    3.771195] DC OR NODE connected to /host1x/sor1
[    3.771445] tegradc tegradc.1: DT parsed successfully
[    3.771492] tegradc tegradc.1: Display dc.ffffff8007400000 registered with id=1
[    3.774474] tegra-i2c 7000c700.i2c: no acknowledge from address 0x50
[    3.775713] tegradc tegradc.1: probed

[    3.874403] tegradc tegradc.1: fb registered

r28.1_nvidia_patch_dc-chg_fdt.log (55.9 KB)
r28.1_nvidia_patch_dc-chg.log (81.1 KB)

Hi mynaemi,

According to your log,

[    2.945073] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000
[    2.945079] tegradc tegradc.0: pclk out of range!

Seems you didn’t modify it correctly, 25.2Mhz represents 640x480 mode. What I mentioned in #10 is to modify the content of “tegra_dc_vga_mode” to that 720x480 mode. You don’t need to change the variable name.

Sorry for misleading.

Hi WayneWWW,

Thanks your reply.

~/kernel/display/drivers/video/tegra/dc/dc.c

I changed the contents of “tegra_dc_vga_mode” to 720 × 480 mode and tried it, but the result did not change.

I attached the modified Makefile, dts file, dc.c file, so is there any incomplete change?

[ChangeFile.zip]
~/hardware/nvidia/platform/t210/jetson/kernel-dts
・Makefile
・tegra210-jetson-cv-base-p2597-2180-a00.dts
・tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts
~/kernel/display/drivers/video/tegra/dc/
・dc.c

[R28.1_patch_dc.c-chg.log]
It will be the log executed by the above change file
ChangeFile.zip (47.8 KB)
r28.1_patch_dc.c-chg.log (81.6 KB)

Hi,

Just check your log again, this is still a vga mode.

[ 2.996975] tegradc tegradc.0: nominal-pclk:25200000 parent:25800000 div:1.5 pclk:17200000 24948000~27468000

Did you rebuild the kernel image the re-flash?

Hi, WayneWWW

I rebuilt the kernel image and reexecuted it.
The pclk error was not output, but it was not displayed on the display.

I attached the log, so do you know something’s wrong?
r28.1_patch_dc.c-chg_1.log (61.1 KB)

Hi mtakahas,

I don’t see this error with my panel, could you check hardware setting first?

[ 9.685226] tegradc tegradc.0: sor_poll_register 0x16: timeout
[ 9.685229] tegradc tegradc.0: dc timeout waiting for HEAD MODE = SLEEP
[ 10.188103] Host read timeout at address 542000e0
[ 10.695091] Host read timeout at address 542000e0

Hi WayneWWW,

Our hardware (include display port and HDMI) operated correctly with modified R24.2.1.
It seems normal.

Can we compare between our kernel files and your kernel files ?

  • Image
  • zImage
  • .dtb / .dts
  • dc.c
  • extlinux.conf

Best Regards,

Hi WayneWWW,

I wrote our procedure in #13.

(4)-(a)

  • Overwrite dtb file
  • flash.sh -r -k DTB jetson-tx1

(4)-(b)

  • Edit extlinux.conf

Is (4)-(b) wrong procedure for R28.1 of JetsonTX1 ?

https://elinux.org/Jetson/TX2_DTB#TX2
Starting on Jetson TX2, the Device Tree Binary (DTB) is no longer specified by default in /boot/extlinux/extlinux.conf. This is to allow u-boot to pass parameter to load the specific DTB file. However if you have compiled your own DTB, there are ways to set it yourself.