March 1, 2023, 12:56pm
I try to run adv7280-m chip on Nano platform.
As for now, I have some errors:
[ +0.201276] video4linux video0: frame start syncpt timeout!0
[ +0.005726] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ +0.000006] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ +0.004901] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ +0.000004] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000040
How to find description of these errors?
How to calculate register from TRM, related to these errors?
March 5, 2023, 3:57pm
Do Nvidia manage drivers/media/platform/tegra/camera/csi/csi2_fops.c file?
How to interpret these status errors?
you may look into the CSI driver for general failures.
int tegra_csi_error(struct tegra_csi_channel *chan, int port_idx)
val = pp_read(port, TEGRA_CSI_PIXEL_PARSER_STATUS);
err |= val & 0x4000;
pp_write(port, TEGRA_CSI_PIXEL_PARSER_STATUS, val);
val = cil_read(port, TEGRA_CSI_CIL_STATUS);
err |= val & 0x02;
cil_write(port, TEGRA_CSI_CIL_STATUS, val);
val = cil_read(port, TEGRA_CSI_CILX_STATUS);
err |= val & 0x00020020;
cil_write(port, TEGRA_CSI_CILX_STATUS, val);
March 6, 2023, 10:00am
I know it.
In my case,
How do I understand the value 0x00000010?
Which is appropriate register in TRM with bit description?
TRM and checking [29.16.25 CSI_CSI_CIL_A_STATUS_0] and also [29.16.26 CSI_CSI_CILA_STATUS_0] for details.
March 6, 2023, 4:06pm
There is no TRM inside download center among documents, related to Nano.
Could you please share it?
please check Tegra X1 TRM, I’ve already link the documentation in my previous post.
March 7, 2023, 10:03am
Thank you for such information.
About my issue.
This is explanation of my errors:
CILA_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11)
instead of transitioning into the Escape mode or Turn Around mode (LP00).
CILA_DATA_LANE0_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a
stop state (LP11) instead of transitioning
What can be reason for it?
Device tree binding?
Thank you a lot for your ideas.
this usually due to sensor side issues, you may examine the sensor configuration.
please dig into TRM, you may check THS_SETTLE to understand the settle time for data lane when moving from LP to HS (i.e. LP11->LP01->LP00)
camera stack attempts to auto-calibrate this by
mclk_multiplier parameter, you may configured this manually by device tree property,
cil_settletime. please see-also
Property-Value Pairs for details.
March 9, 2023, 3:44pm
As a result, issue was related to the Nvidia SoM board, maybe it was damaged.
I’ve replaced it on another one and now it works.
After it, I ported driver and device tree to Xavier NX platform.
The image from analog input was corrupted. I’ve found, that bytesperline should be atom (64-Byte) aligned.
By default its value is 1440.
Where this value is stored? Device tree or kernel code?
it came from device tree property settings.
but… you may enable
v4l2-ctl command to adjust the stride by
March 10, 2023, 9:03am
I can not find this property, could you please show me the place where it stored.
I attached modified device tree for adv7280-m.
tegra210-camera-rbpcv2-dual-adv7280m.dtsi (6.8 KB)
which Jetpack release you’re using? this control property,
--preferred_stride should be included in the latest release. i.e. Jetpack-4.6.3.
you may running
v4l2-ctl --all for checking.
March 13, 2023, 7:30am
I use L4T 32.6.1 release.
But my question was, how to set this parameter via device tree?
March 13, 2023, 7:33am
And another one issue, related to CSI.
I’ve got the video, but it is “shaking” up and down
Could you please advise me, what it can be a reason for it?
--preferred_stride is the control property through command-line. it’s used to override the stride settings, which is calculated by sensor’s active width.
regarding to this “shaking” issue.
is your driver output the video frames as interleave or progressive?
March 14, 2023, 7:54am
I tried both video output: interleave and progressive, results are the same.
Please take a look to this video. I’ve activated border pattern on ADV side.
Maybe, it can help to understand the reason of issue.
may I know what’s the ground truth it is, or, what’s the sources image looks like.
is there a frame-drop? what’s the output fps results?
March 14, 2023, 8:47am
I don’t know, how source image looks like.
I’ve activated boundary box test pattern inside adv7180 chip.
How to check it?
I also don’t know how to check it, please advise.
may I know what’s your capture pipeline?
here’s gst pipeline to disable preview and shows frame-rate only.
$ gst-launch-1.0 nvarguscamerasrc sensor-id=0 ! 'video/x-raw(memory:NVMM),width=1920, height=1080, framerate=30/1, format= NV12' ! nvvidconv ! 'video/x-raw(memory:NVMM),format=I420' ! fpsdisplaysink text-overlay=0 video-sink=fakesink sync=0 -v
if you’re using gst pipeline,
please refer to above, by adding
fpsdisplaysink to enable frame-rate checking.