I try to capture a video node of interlaced PAL(720x288-50 fps) video frames using custom carrier board(fpga and tx2 core board).
We want before GPU processing frames, convert it to De-interlace frame(progressive frame-720*576-25fps).
Is the de-interlacing feature in TX2 hardware suitable for this task?
If yes, how do you suggest I use it?
if no,what is your solution?
Also, the link provided in this thread is broken !!
Please Answer Me!!!
We don’t have existing implementation for de-interlacing. One possible solution is to leverage GPU through CUDA code. If your source supports V4L2, you may refer to
The sample demonstrates allocating CUDA buffers and capturing frames through V4l2. FYR.
Can you Guide me about VIC(VIDEO IMAGE COMPOSITOR) Unit in TX2 TRM CHAPTER 21,based TRM Reference,
De-interlacing is one of features of TX2 VIC Unit,
whether for this operation exist sample ??
What do you think about nvcompositor( Nvidia hardware accelerated Gstreamer plugins)?
The hardware VIC engine has the capability but we don’t have software implementation of inputting interlaced frames and outputting progressive frames. There are many interlaced-encoded video stream, so we implement auto de-interlacing in video decoding.
None of the Jetson family hardware, such as the AGX, has implemented this software feature ??