Deskew didn't improve the D-PHY lane clock performance

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

I downloaded firmware from this topic, and updated.
https://forums.developer.nvidia.com/t/issue-with-deskew-calibration-on-agx-orin/325872
AGX Orin, R36.3.0.

00deskew
00deskew1220×235 57.8 KB

the highest lane clock is able to (0x19,0x15,0x19,0x19)*100Mhz without deskew.
after enabling deskew, i checked the debug message, deskew worked.
but the highest lane clock is still (0x19,0x15,0x19,0x19)*100Mhz

May i know what’s the problem?
thank you.

3

hello dennis.hu,

may I know what’s the clock performance you’re going to improve?

according to developer guide, SerDes Pixel Clock,
let me re-cap as below..

skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.

BTW,
there’re some PHY_INTR has reported within your snapshots.
the error code 0xE000000 which might due to DPHY deskew calibration not complete, it happened when the calibration sequence length is not long enough. please give it a try to configure cil_settletime, and please also review the serdes_pix_clk_hz settings.
you may see-also TRM for the register description, such as.. CILA_INTR_0_STATUS_CILA_0

7

serdes_pix_clk_hz = “625000000”;
num-lanes = "4’;
expected lane date is 2.5Gbps.
the mipi clock is 2.5Ghz.
if i set the data rate to 0x19 (x100MHz), 2.5Gbps.
the VI will not capture full frame, many error occurred.
the highest data rate could be set to 2.3Gbps.

I tried to change ‘cil_settletime’ from ‘0’ to ‘0x400’, the error message is same.
I also tried different deskew width, nothing changed.

8

I changed the cil_settletime to ‘0x400’.
here is the error message.
kworker/2:2-214 [002] … 330.934929: rtcpu_nvcsi_intr: tstamp:10923089163 class:GLOBAL type:PHY_INTR0 phy:2 cil:1 st:0 vc:0 status:0x00000040
kworker/2:2-214 [002] … 330.934930: rtcpu_nvcsi_intr: tstamp:10923089163 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:4 vc:0 status:0x00000004
kworker/2:2-214 [002] … 330.934930: rtcpu_string: tstamp:10923090132 id:0x04010000 str:"ISR PHY 2 CIL_B 0x40

9

hello dennis.hu,

may I double check the data-rate of your camera use-case?
for instance.. is it 2.5Gbps per lane?

10

I’m using IMX490 w/ ISP camera for the testing.
The datarate will less than 2.5Gbps per lane.
but discontinous_clk = “yes” has been set.
here is more details about device tree.
mclk_khz = “24000”;
// num_lanes = “4”;
num_lanes = “4”;
tegra_sinterface = “serial_a”;
vc_id = “0”;
discontinuous_clk = “yes”;
dpcm_enable = “false”;
cil_settletime = “0x400”;
dynamic_pixel_bit_depth = “8”;
csi_pixel_bit_depth = “8”;
mode_type = “yuv”;
pixel_phase = “uyvy”;

				active_w = "3840";
				active_h = "2160";
				readout_orientation = "0";
				line_length = "4000";
				inherent_gain = "1";
				pix_clk_hz = "100000000"; 
				set_mode_delay_ms = "100";
			        serdes_pix_clk_hz = "625000000";

serdes_pix_clk_hz = (deserializer output data rate in hertz) * (number of CSI lanes) / (bits per pixel).
= 2.5Ghz * 4 / 16 = 625000000.
if i set the output rate to 2.5Ghz, failed to capture full frame due to many errors.
if i set the output rate to 2.4Ghz, succeed to capture full frame, but the image has issue. The image has a border effect.
if i set the output rate to 2.3Ghz, succeed to capture full frame, it works well.

11

if i set cil_settletime to ‘0’.
the maximum output rate is 2.1Ghz.

12

hello dennis.hu,

please try setting serdes_pix_clk_hz to 1250000000 for testing.

13

it works. Jerry, thank you so much!

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