DSI bring-up

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

Hi,

I am currently working on DSI display bring-up with Jetson Nano SoM. Here I am using OSD(HX8394) DSI display which have 800x1280 resolutions.

I have made below changes in device tree.
panel-a-wxga-8-0.dtsi (19.4 KB)
tegra210-porg-p3448-common.dtsi (37.5 KB)

Below file contains the dmesg logs to identify if anything which we are missing.
dmesg.txt (65.6 KB)

After this, we are not able to detect the DSI display in display settings page.

Can you please help me out to resolve this issue? I do not have more idea about where we have to check.

Also we verified, After making changes in device tree, panel-a-1200-800-8-0.c file will be called. I added debug logs to identify.

Thanks

3

please refer to

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Hello @WayneWWW ,

Thank You for the reply. I already reviewed the mentioned thread, and as per that thread, I made changes in device tree file. After those changes, I am not able to detect the DSI display. As well as we verified the power up sequence of the DSI display, which also seems okay.

After making all changes, I am not able to identify the display detection. I already attached our changes above. Can you please help me to identify the RCA for the same?

Thanks

6

Is there any update ?

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Hi Eema,
we had similar issues with a similar display and we just managed to get it working. In the end, the issue was one wrong byte in the init sequence of the display controller (the byte which sets how many data lanes are used, which was, of course, undocumented in the datasheet). After changing that, it worked like a charm. So I really can recommend reviewing the init sequence carefully…

One other thing I noticed in your panel specification is your clock-frequency (aka pclk) in the display-timings section:

display-timings {
        800x1280-32 {
                clock-frequency = <57000000>;
                hactive = <800>;
                vactive = <1280>;
                hfront-porch = <90>;
                hback-porch = <90>;
                hsync-len = <30>;
                vfront-porch = <112>;
                vback-porch = <15>;                                       
                vsync-len = <4>;
                nvidia,h-ref-to-sync = <4>;
                nvidia,v-ref-to-sync = <1>;
        };
};

For the given parameters, it seems too low with the set 57MHz to reach 60Hz framerate. Afaik you should set it to (800+90+90+30)Ă—(1280+112+15+4)Ă—60 = 85506600 Hz.

And I also would not define the reset gpio directly in the panel specification, as this is a platform property.

nvidia,panel-rst-gpio = <&gpio 149 GPIO_ACTIVE_HIGH>;

I’d rather (re)define it in the board dts :

host1x {
		/* DSI mapped to tegradc.1 */
		dc@54240000 {
			status = "okay";
			nvidia,dc-or-node = "/host1x/dsi";
			nvidia,dc-connector = <&dsi>;
			/* DSI supplies */
			avdd_dsi_csi-supply = <&max77620_sd3>;
			avdd_lcd-supply = <&battery_reg>;
			dvdd_lcd-supply = <&battery_reg>;
			vdd_lcd_bl_en-supply = <&battery_reg>;
			vdd_lcd_bl-supply = <&battery_reg>;
		};

		dsi {
			nvidia,dsi-controller-vs = <DSI_VS_1>;
			status = "okay";
			nvidia,active-panel = <&panel_a_wxga_8_0>;
			nvidia,dsi-csi-loopback;
			panel-a-wxga-8-0 {
				status = "okay";
				nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
				/* Only 2 lanes used on Porg */
				nvidia,dsi-n-data-lanes = <2>;
			};
		};
	};

Apart from that your dmesg output looks alright. Hope this helps.
And if you haven’t already, I’d recommend checking if the init sequence is transmitted correctly in the LP mode with a logic analyzer.

Franz

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