Hello ,
I am looking for a 2 lane Display which has driver compatability with our Nvidia (Nano platform).
Please help me with the display part number and its driver location.
I came across with these , but not sure if these are compatible (driver) with our nvidia …
Hello,
Thank you for sharing that thread, but i did not found any 2x lane display which is compatible with nvidia source code.
Actually we are designing a custom carrier board , and their we want to test DSI port of NANO SoM , Hence please suggest any 2lane display compatible with nvidia platform.
You have asked this question 3 times.
There is no direct answer to your question.
We have no restriction about something can work or cannot work over the DSI. You can check any DSI panel from any vendor if they say it can support 2 lanes case. And this vendor should provide their panel spec and the driver code.
NVIDIA does not manufacture panel, so it is not possible for us to provide panel driver code for your case. We only provide DSI driver code and it will use callback function from your panel driver to enable it.
If you don’t know how to register the vendor’s driver code to DSI as callback, then it is the question I can reply.
But if you just ask for panel resources, then it is not what I can help.
Hello @WayneWWW Sir,
Thank you for making things clear.
Now i have one driver with me
linux/panel-ilitek-ili9881c.c at rpi-4.20.y · raspberrypi/linux · GitHub
Could you please help me with the steps involved for the integration of this driver with our Nvidia source code. “How to register the vendor’s driver code to DSI as callback”
Thanks
Please refer to this post.
Hello Sir ,
After refering the Above Post suggested by you.
I made the following changes , but i am not sure whether it will work for not . Please review and suggest , how should i proceed further
~/Vinay/VKSINGH_GIT/kernel/Linux_for_Tegra/source/public/kernel/nvidia/drivers/video/tegra/dc/panel vi panel-ilitek-ili9881c.c
MODIFIED MAKEFILE
admin@vm97:~/Vinay/VKSINGH_GIT/kernel/Linux_for_Tegra/source/public/kernel/nvidia/drivers/video/tegra/dc/panel$ vi Makefile
GCOV_PROFILE_panel-ilitek-ili9881c.o := n
obj-y += panel-ilitek-ili9881c.o
MODIFIED panel-a-wxga-8-0.dtsi
admin@vm97:~/Vinay/VKSINGH_GIT$ git diff kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
diff --git a/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi b/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
index 302cce122…a3b1318c8 100644
— a/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
+++ b/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
@@ -27,7 +27,7 @@
status = “disabled”;
compatible = “a,wxga-8-0”;
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <4>;
nvidia,dsi-n-data-lanes = <2>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
@@ -37,6 +37,7 @@
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
/*
nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0xf0 0x5a 0x5a 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 5>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0 CMD_NOT_CLUBBED>,
@@ -45,7 +46,216 @@
<TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x4 0x0 0x0 0xc3 0x40 0x00 0x28 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 170>;
nvidia,dsi-n-init-cmd = <8>;
*/
/*nvidia,dsi-n-init-cmd = <10>;*/
nvidia,dsi-init-cmd = <TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE1 0x93 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE2 0x65 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE3 0xF8 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x3C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x3C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x74 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0xF7 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0xF7 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0xF1 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x23 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x09 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x70 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0xFF 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0xFF 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x7F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0xA0 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x1E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x0B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x45 0x28 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0xA9 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x59 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5A 0x2D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5B 0x1A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5C 0x15 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5D 0x7F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5E 0x69 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5F 0x59 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x4C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x47 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x38 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x3D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x27 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x41 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x5B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x46 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6A 0x49 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6B 0x3A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6C 0x34 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6D 0x25 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6E 0x15 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6F 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x70 0x7F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x71 0x69 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x72 0x59 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x73 0x4C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x74 0x47 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0x38 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x3D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x27 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x41 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x79 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7A 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7B 0x5B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7C 0x46 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7D 0x49 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7E 0x3A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7F 0x34 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x25 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x81 0x15 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x82 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x50 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x02 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x52 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x77 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x05 0x57 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x06 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x07 0x4E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x08 0x4C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0A 0x4A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0B 0x48 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0D 0x46 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x44 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0F 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x10 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x12 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x13 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x14 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x15 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x16 0x51 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x53 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x77 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0x57 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1D 0x4F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1E 0x4D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1F 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x20 0x4B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x21 0x49 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x22 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x23 0x47 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0x45 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x25 0x41 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x26 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x27 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x28 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2A 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2B 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2C 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2D 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2E 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2F 0x13 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x30 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x32 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x33 0x0D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x34 0x0F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x07 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x09 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x0B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3B 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x42 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x45 0x12 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x46 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x47 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x48 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x49 0x0C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4A 0x0E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4B 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4C 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4D 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4E 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4F 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4F 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x54 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x56 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x58 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5B 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5C 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5D 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5E 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5F 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x03 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x75 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0xB4 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6A 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6B 0x0C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6D 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6E 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6F 0x88 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0xBB 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x2A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x48 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2B 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2D 0x03 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2E 0x03 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 120>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 5>;
nvidia,dsi-n-init-cmd = <202>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <107>;
nvidia,active-panel = <&panel_a_wuxga_8_0>;
nvidia,active-panel = <&panel_a_wxga_8_0>;
nvidia,dsi-csi-loopback;
panel-a-wuxga-8-0 {
status = "okay";
config TEGRA_DSI
bool “Enable DSI panel.”
depends on TEGRA_DC && TEGRA_MIPI_CAL
default y
help
Say Y here to enable the DSI panel.
Please review the changes…
Please clean up the patch format first. Looks like it get messed up when putting it on forum.
Sure sir,
Hello Sir ,
After refering the Above Post suggested by you.
I made the following changes , but i am not sure whether it will work for not . Please review and suggest , how should i proceed further
~/Vinay/VKSINGH_GIT/kernel/Linux_for_Tegra/source/public/kernel/nvidia/drivers/video/tegra/dc/panel vi panel-ilitek-ili9881c.c
MODIFIED MAKEFILE
admin@vm97:~/Vinay/VKSINGH_GIT/kernel/Linux_for_Tegra/source/public/kernel/nvidia/drivers/video/tegra/dc/panel$ vi Makefile
GCOV_PROFILE_panel-ilitek-ili9881c.o := n
obj-y += panel-ilitek-ili9881c.o
MODIFIED , panel-a-wxga-8-0.dtsi
“As per changes suggested by How to enable MIPI DSI display? - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums”
vi kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
MODIFIED DTS file tegra210-p3448-0000-p3449-0000-b00-hdmi-dsi.dts
admin@vm97:~/Vinay/VKSINGH_GIT/kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/t210/porg/kernel-dts$ vi tegra210-p3448-0000-p3449-0000-b00-hdmi-dsi.dts
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = "okay";
/*nvidia,active-panel = <&panel_a_wuxga_8_0>;*/removed
nvidia,active-panel = <&panel_a_wxga_8_0>;//added
nvidia,dsi-csi-loopback;
panel-a-wuxga-8-0 {
status = "okay";
Please review the changes…
Please check the panel driver under kernel/nvidia/drivers/video/tegra/dc/panel/./panel-a-1200-800-8-0.c.
Your panel driver needs to have such form. You cannot just copy & paste panel-ilitek-ili9881c.c.
And I don’t know what did you change here.
- MODIFIED , panel-a-wxga-8-0.dtsi
“As per changes suggested by How to enable MIPI DSI display? - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums”
vi kernel/Linux_for_Tegra/source/public/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-a-wxga-8-0.dtsi
Again, you cannot just copy and paste what that post gave you. You need to write the correct DSI commands that matches to your panel.
- ADDED default y in Kconfig
admin@vm97:~/Vinay/VKSINGH_GIT/kernel/Linux_for_Tegra/source/public/kernel/nvidia/drivers/video/tegra vi Kconfig
comment “NVIDIA Tegra Display Driver options”
config TEGRA_NVDISPLAY
bool “Tegra NvDisplay Architecture Support”
depends on TEGRA_DC
default y
help
Enable the support for NvDisplay Architecture
If unsure, say N
config TEGRA_DSI
bool “Enable DSI panel.”
depends on TEGRA_DC && TEGRA_MIPI_CAL
default y
help
Say Y here to enable the DSI panel.
This is not needed. It should be enabled by default.
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = “okay”;
/nvidia,active-panel = <&panel_a_wuxga_8_0>;/removed
nvidia,active-panel = <&panel_a_wxga_8_0>;//added
nvidia,dsi-csi-loopback;
panel-a-wuxga-8-0 {
status = “okay”;
Please create a new panel node and using panel_a_wxga_8_0 as a template to write a new dsi node.
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