Hi my hardware engineers are having a couple issues they are working through and would like if you could help perhaps.
Switching modes between SPI and GPIO, without changing the device tree.
Activation of the ST7701S(MIPI-DSI) display driver (available in the Linux kernel), but there is no activation in the menu config
Can you give guidance on this? Much appreciated.
Hi xtianus,
For this use case, you could just modify the pinmux register to desired function (SPI or GPIO) dynamically.
You could refer to the porting guide from your vendor for the display.
If you want to modify the kernel config, please refer the following instruction to re-build the kernel.
NVIDIA Jetson Linux Developer Guide : Kernel Customization | NVIDIA Docs
Hi @KevinFFF,
Here is the response from engineer.
We have a MIPI DSI panel with ST7701s driver. So, before integrate driver to the kernel, I used make menuconfig to configured mipi. Before I include the option <> NVIDIA Tegra DRM , image could build successfully. I get errors in nvidia code. However, when I include the option <> NVIDIA Tegra DRM and exit with save, it couldn’t build successfully. So I disinclude it again, it couldn’t build successfully anyway. How to set the display correctly?"
Hi,
This is not the correct way to enable MIPI DSI within jetson platform.
NVIDIA Tegra DRM is totally not in use on jetson nano.
I would suggest you can check posts in TX1 forum for this because we actually seldom enable DSI on Jetson nano platform.
Hi Wayne, The jetson Nano is our choice because of 2 reasons Size and Cost. Do you have, or would you suggest that we move on to the Orin SOM? I believe it has similar sizing. Would you say it has better DSI support? If it’s highly recommended we could perhaps switch but that would be a great cost right at the exact moment because our BOM is based on the Nano.
If you could help where needed it would be greatly appreciated as our device has a very specific size use case and we have custom heat sinks and everything so the new Orin size could be fine but the question becomes is the same issue with the Orin as is with the Nano now?
Hi,
Orin and Xaiver totally do not support DSI anymore. So using them does not help.
We have some old posts here. You could refer to the dts tegra210-p3448-0000-p3449-0000-b00-hdmi-dsi.dts to check how to enable “dsi” in our tegradc controller.
Hi Wayne,
I am an engineer, who works with this MIPI DSI display.
I tried to set up dsi according to your link post. However, I am getting a problem when starting the kernel.
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.9.337-tegra (buildbrain@mobile-u64-5434-d8000) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05) ) #1 SMP PREEMPT Thu Jun 8 21:19:14 PDT 2023
[ 0.000000] Boot CPU: AArch64 Processor [411fd071]
[ 0.000000] OF: fdt:memory scan node memory@80000000, reg size 32,
[ 0.000000] OF: fdt: - 80000000 , 7ee00000
[ 0.000000] OF: fdt: - 100000000 , 7f200000
[ 0.000000] Found tegra_fbmem: 00800000@92cb4000
[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000070006000 (options '')
[ 0.000000] bootconsole [uart8250] enabled
[ 1.363225] imx219 7-0010: imx219_board_setup: error during i2c read probe (-121)
[ 1.363295] imx219 7-0010: board setup failed
[ 1.387145] imx219 8-0010: imx219_board_setup: error during i2c read probe (-121)
[ 1.387205] imx219 8-0010: board setup failed
[ 9.570207] Host write timeout at address 54300028
[ 11.077725] Host read timeout at address 542000dc
[ 11.077727] Host write timeout at address 542000dc
[ 19.619504] Host read timeout at address 54200104
[ 19.619507] Host write timeout at address 542000e0
[ 33.688188] Host write timeout at address 54300028
[ 41.225002] INFO: rcu_preempt self-detected stall on CPU
[ 41.225009] INFO: rcu_preempt self-detected stall on CPU
[ 41.225009] 0-...: (2 ticks this GP) idle=d79/140000000000002/0 softirq=363/363 fqs=0
[ 41.225015]
[ 41.225015] 2-...: (1 ticks this GP) idle=71f/140000000000001/0 softirq=228/228 fqs=0
[ 41.225021]
[ 41.225021] rcu_preempt kthread starved for 5276 jiffies! g18446744073709551441 c18446744073709551440 f0x0 RCU_GP_WAIT_FQS(3) ->state=0x1
[ 41.225028] rcu_preempt kthread starved for 5276 jiffies! g18446744073709551441 c18446744073709551440 f0x0 RCU_GP_WAIT_FQS(3) ->state=0x1
[ 41.727460] INFO: rcu_preempt detected stalls on CPUs/tasks:
[ 41.727476] 0-...: (2 ticks this GP) idle=d79/140000000000002/0 softirq=363/363 fqs=0
[ 41.727484] 2-...: (1 ticks this GP) idle=71f/140000000000001/0 softirq=228/228 fqs=0
[ 41.727494]
[ 56.801048] BUG: workqueue lockup - pool cpus=0-3 flags=0x5 nice=-20 stuck for 53s!
[ 94.987440] Host read timeout at address 54200d98
[ 94.987442] Host write timeout at address 54300028
[ 105.036526] Host read timeout at address 542000e0
[ 105.538997] Host write timeout at address 54300028
[ 122.120137] Host read timeout at address 54200104
[ 122.120140] Host write timeout at address 54300028
[ 129.154489] Host write timeout at address 54300028
[ 136.188841] Host write timeout at address 54300028
[ 143.223241] Host write timeout at address 54300028
[ 151.765122] Host read timeout at address 542000e0
[ 151.765125] Host write timeout at address 542000dc
[ 154.277465] Host read timeout at address 542000dc
[ 154.277467] Host write timeout at address 542000dc
[ 180.405157] Host read timeout at address 54200104
[ 180.405159] Host write timeout at address 54300028
[ 192.966490] Host write timeout at address 54300028
[ 193.971415] Host write timeout at address 54300028
[ 220.099003] INFO: rcu_preempt detected stalls on CPUs/tasks:
[ 220.099009] 2-...: (1 ticks this GP) idle=723/140000000000001/0 softirq=236/236 fqs=4
[ 220.099014] (detected by 3, t=10049 jiffies, g=-172, c=-173, q=7)
[ 220.099048] rcu_preempt kthread starved for 6407 jiffies! g18446744073709551444 c18446744073709551443 f0x2 RCU_GP_WAIT_FQS(3) ->state=0x1
[ 240.197198] Host read timeout at address 542000dc
[ 240.197200] Host write timeout at address 54300028
[ 243.714462] Host read timeout at address 542000dc
[ 243.714465] Host write timeout at address 542000dc
[ 260.295457] INFO: rcu_preempt detected stalls on CPUs/tasks:
[ 260.295463] 2-...: (1 ticks this GP) idle=723/140000000000001/0 softirq=238/238 fqs=1
[ 260.295467] (detected by 1, t=5904 jiffies, g=-171, c=-172, q=6)
[ 260.295495] rcu_preempt kthread starved for 4648 jiffies! g18446744073709551445 c18446744073709551444 f0x2 RCU_GP_WAIT_FQS(3) ->state=0x0
Here is my device tree arch/arm64/boot/dts/tegra210-porg-p3448-common.dtsi
host1x {
/* Camera unit clocks */
assigned-clocks = <&tegra_car TEGRA210_CLK_EXTERN3>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_VI_I2C>,
<&tegra_car TEGRA210_CLK_CLK_OUT_3_MUX>,
<&tegra_car TEGRA210_CLK_VI>,
<&tegra_car TEGRA210_CLK_ISP>,
<&tegra_car TEGRA210_CLK_ISPB>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_EXTERN3>,
<&tegra_car TEGRA210_CLK_PLL_C>,
<&tegra_car TEGRA210_CLK_PLL_C>,
<&tegra_car TEGRA210_CLK_ISP>;
assigned-clock-rates = <24000000>,
<102000000>,
<102000000>,
<102000000>,
<102000000>,
<24000000>,
<408000000>,
<408000000>,
<0>;
/* tegradc.0 */
dc@54200000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,cmu-enable = <1>;
nvidia,fb-bpp = <32>; /* bits per pixel */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
nvidia,dc-or-node = "/host1x/sor1";
nvidia,dc-connector = <&sor1>;
win-mask = <0x7>; /* Assign only wins A/B/C */
};
dc@54240000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,fb-bpp = <32>;
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
nvidia,dc-or-node = "/host1x/dsi";
nvidia,dc-connector = <&dsi>;
/* DSI supplies */
avdd_dsi_csi-supply = <&max77620_sd3>;
avdd_lcd-supply = <&battery_reg>;
dvdd_lcd-supply = <&battery_reg>;
vdd_lcd_bl_en-supply = <&battery_reg>;
vdd_lcd_bl-supply = <&battery_reg>;
win-mask = <0x7>; /* Assign only wins A/B/C */
};
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = "okay";
nvidia,active-panel = <&panel_a_wxga_8_0>;
nvidia,dsi-csi-loopback;
panel-a-wxga-8-0 {
status = "okay";
/* Only 2 lanes used on Porg */
nvidia,dsi-n-data-lanes = <2>;
};
sor1 {
/* Compared to Jetson-TX1's baseboard (P2597), HDMI TX
* lanes 0 and 2 have been swapped in Porg's baseboard
* (P3448) making it a straight lane mapping between
* SOR1 and the pad.
*/
nvidia,xbar-ctrl = <0 1 2 3 4>;
status = "okay";
hdmi-display {
status = "okay";
};
};
dpaux {
status = "okay";
};
dpaux1 {
status = "okay";
};
};
backlight {
compatible = "pwm-backlight";
status = "okay";
panel-a-wxga-8-0-bl {
status = "okay";
pwms = <&tegra_pwm 0 40161>;
};
};
If I comment out the parameter “nvidia,fb-bpp = <32>;” the system starts up, but in dmesg it says that dsi does not start because this parameter is missing.
What could be the problem?
Use dmesg to check the log instead of uart. Also, check the panel driver to meet your panel requirement.
There should be something called panel-a-wxga-8-0.c (or similar file name) under your kernel source (nvidia directory).
There is no standard answer for a DSI panel. For example, I am not sure if it is okay to set all the regulator here to be dummy one for your panel.
avdd_lcd-supply = <&battery_reg>;
dvdd_lcd-supply = <&battery_reg>;
vdd_lcd_bl_en-supply = <&battery_reg>;
vdd_lcd_bl-supply = <&battery_reg>;
I am used example from the arch/arm64/boot/dts/tegra210-p3448-0000-p3449-0000-b00-hdmi-dsi.dts
/ {
nvidia,dtsfilename = __FILE__;
host1x {
/* DSI mapped to tegradc.1 */
dc@54240000 {
status = "okay";
nvidia,dc-or-node = "/host1x/dsi";
nvidia,dc-connector = <&dsi>;
/* DSI supplies */
avdd_dsi_csi-supply = <&max77620_sd3>;
avdd_lcd-supply = <&battery_reg>;
dvdd_lcd-supply = <&battery_reg>;
vdd_lcd_bl_en-supply = <&battery_reg>;
vdd_lcd_bl-supply = <&battery_reg>;
};
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = "okay";
nvidia,active-panel = <&panel_a_wxga_8_0>;
nvidia,dsi-csi-loopback;
panel-a-wxga-8-0 {
status = "okay";
/* Only 2 lanes used on Porg */
nvidia,dsi-n-data-lanes = <2>;
};
};
};
backlight {
compatible = "pwm-backlight";
status = "okay";
panel-a-wxga-8-0-bl {
status = "okay";
pwms = <&tegra_pwm 0 40161>;
};
};
};
Also, this is my panel-a-wxga-8-0.dtsi
#include <dt-bindings/display/tegra-dc.h>
#include <dt-bindings/display/tegra-panel.h>
/ {
host1x {
dsi {
panel_a_wxga_8_0: panel-a-wxga-8-0 {
status = "disabled";
compatible = "a,wxga-8-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <2>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
/*
nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0xf0 0x5a 0x5a 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 5>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0 CMD_NOT_CLUBBED>,
<TEGRA_DSI_DELAY_MS 5>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0 CMD_NOT_CLUBBED>,
<TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x4 0x0 0x0 0xc3 0x40 0x00 0x28 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 170>;
*/
nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x13>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xEF 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x10>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC0 0x3B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC1 0x10 0x0C>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC2 0x07 0x0A>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC7 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xCC 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xB0 0x05 0x12 0x98 0x0E 0x0F 0x07 0x07 0x09 0x09 0x23 0x05 0x52 0x0F 0x67 0x2C 0x11>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xB1 0x0B 0x11 0x97 0x0C 0x12 0x06 0x06 0x08 0x08 0x22 0x03 0x51 0x11 0x66 0x2B 0x0F>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x11>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB0 0x5D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB1 0x35 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB2 0x81 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB3 0x80 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB5 0x4E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB7 0x85 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB8 0x20 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC1 0x78 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC2 0x78 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xD0 0x88 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE0 0x00 0x00 0x02>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE1 0x06 0x30 0x08 0x30 0x05 0x30 0x07 0x30 0x00 0x33 0x33>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE2 0x11 0x11 0x33 0x33 0xF4 0x00 0x00 0x00 0xF4 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE3 0x00 0x00 0x11 0x11>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE4 0x44 0x44>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE5 0x0D 0xF5 0x30 0xF0 0x0F 0xF7 0x30 0xF0 0x09 0xF1 0x30 0xF0 0x0B 0xF3 0x30 0xF0>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE6 0x00 0x00 0x11 0x11>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE7 0x44 0x44>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE8 0x0C 0xF4 0x30 0xF0 0x0E 0xF6 0x30 0xF0 0x08 0xF0 0x30 0xF0 0x0A 0xF2 0x30 0xF0>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE9 0x36 0x01>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xEB 0x00 0x01 0xE4 0xE4 0x44 0x88 0x40>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xED 0xFF 0x10 0xBF 0x76 0x54 0x2A 0xFC 0xFF 0xFF 0xCF 0xA2 0x45 0x67 0xFB 0x01 0xFF>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xEF 0x08 0x08 0x08 0x45 0x3F 0x54>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 120>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x66 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x00 0x00>;
/*
nvidia,dsi-init-cmd = <TEGRA_DSI_DELAY_MS 200>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x10>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xB0 0x00 0x11 0x16 0x0E 0x11 0x06 0x05 0x09 0x08 0x21 0x06 0x13 0x10 0x29 0x31 0x18>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xB1 0x00 0x11 0x16 0x0E 0x11 0x07 0x05 0x09 0x09 0x21 0x05 0x13 0x11 0x2A 0x31 0x18>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x11>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB0 0x6D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB1 0x37 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB2 0x81 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB3 0x80 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB5 0x43 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB7 0x85 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB8 0x20 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC1 0x78 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC2 0x78 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC3 0x8C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xD0 0x88 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE0 0x00 0x00 0x02>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE1 0x03 0xA0 0x00 0x00 0x04>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xA0 0x00 0x00 0x00 0x20 0x20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE3 0x00 0x00 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE4 0x22 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE5 0x05 0xEC 0xA0 0xA0 0x07 0xEE 0xA0 0xA0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE6 0x00 0x00 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE7 0x22 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE8 0x06 0xED 0xA0 0xA0 0x08 0xEF 0xA0 0xA0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xEB 0x00 0x00 0x40 0x40 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xED 0xFF 0xFF 0xFF 0xBA 0x0A 0xBF 0x45 0xFF 0xFF 0x54 0xFB 0xA0 0xAB 0xFF 0xFF>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xEF 0x10 0x0D 0x04 0x08 0x3F 0x1F>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x13>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xEF 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x77 0x01 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x66 0x00>,
<TEGRA_DSI_DELAY_MS 50>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 50>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x00 0x00>;
*/
nvidia,dsi-n-init-cmd = <41>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <107>;
nvidia,out-height = <172>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <800>;
nvidia,out-yres = <1280>;
};
/*
display-timings {
800x1280-32 {
clock-frequency = <74880000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <24>;
hback-porch = <132>;
hsync-len = <4>;
vfront-porch = <8>;
vback-porch = <8>;
vsync-len = <4>;
nvidia,h-ref-to-sync = <4>;
nvidia,v-ref-to-sync = <1>;
};
};
*/
display-timings {
800x1280-32 {
clock-frequency = <25000000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <140>;
hback-porch = <160>;
hsync-len = <8>;
vfront-porch = <20>;
vback-porch = <20>;
vsync-len = <8>;
nvidia,h-ref-to-sync = <4>;
nvidia,v-ref-to-sync = <1>;
};
};
cmu {
nvidia,cmu-csc = < 0x138 0x3ba 0x00d
0x3f5 0x120 0x3e6
0x3fe 0x3f8 0x0e9 >;
nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6
7 8 9 10 11 11 12 13
13 14 15 15 16 17 17 18
18 19 19 20 20 21 21 22
22 23 23 23 24 24 24 25
25 25 26 26 26 27 27 27
28 28 28 28 29 29 29 29
30 30 30 30 31 31 31 31
32 32 32 32 33 33 33 33
34 34 34 35 35 35 35 36
36 36 37 37 37 37 38 38
38 39 39 39 39 40 40 40
41 41 41 41 42 42 42 43
43 43 43 44 44 44 45 45
45 45 46 46 46 46 47 47
47 47 48 48 48 48 49 49
49 49 50 50 50 50 50 51
51 51 51 52 52 52 52 52
53 53 53 53 53 53 54 54
54 54 54 55 55 55 55 55
55 56 56 56 56 56 56 57
57 57 57 57 57 57 58 58
58 58 58 58 59 59 59 59
59 59 59 60 60 60 60 60
60 60 61 61 61 61 61 61
61 62 62 62 62 62 62 62
63 63 63 63 63 63 63 64
64 64 64 64 64 64 65 65
65 65 65 65 66 66 66 66
66 66 66 67 67 67 67 67
67 68 68 68 68 68 68 69
69 69 69 69 69 70 70 70
70 70 70 71 71 71 71 71
71 72 72 72 72 72 72 73
73 73 73 73 73 74 74 74
74 74 74 74 75 75 75 75
75 75 76 76 76 76 76 76
77 77 77 77 77 77 77 78
78 78 78 78 78 79 79 79
79 79 79 79 80 80 80 80
80 80 80 80 81 81 81 81
81 81 81 82 82 82 82 82
82 82 82 83 83 83 83 83
83 83 83 83 84 84 84 84
84 84 84 84 85 85 85 85
85 85 85 85 85 85 86 86
86 86 86 86 86 86 86 86
87 87 87 87 87 87 87 87
87 87 88 88 88 88 88 88
88 88 88 88 88 88 89 89
89 89 89 89 89 89 89 89
89 89 90 90 90 90 90 90
90 90 90 90 90 90 91 91
91 91 91 91 91 91 91 91
91 91 91 92 92 92 92 92
92 92 92 92 92 92 92 92
93 93 93 93 93 93 93 93
93 93 93 93 93 93 94 94
94 94 94 94 94 94 94 94
94 94 94 94 95 95 95 95
95 95 95 95 95 95 95 95
95 96 96 96 96 96 96 96
96 96 96 96 96 96 97 97
97 97 97 97 97 97 97 97
98 99 99 100 101 101 102 103
103 104 105 105 106 107 107 108
109 110 110 111 112 112 113 114
114 115 115 116 117 117 118 119
119 120 120 121 121 122 123 123
124 124 125 125 126 126 127 128
128 129 129 130 130 131 131 132
132 133 133 134 134 135 135 136
136 137 138 138 139 139 140 140
141 141 142 142 143 143 144 144
144 145 145 146 146 147 147 148
148 149 149 150 150 151 151 152
152 153 153 153 154 154 155 155
156 156 157 157 157 158 158 159
159 160 160 160 161 161 162 162
162 163 163 164 164 164 165 165
165 166 166 167 167 167 168 168
168 169 169 169 170 170 171 171
171 172 172 172 173 173 173 174
174 174 175 175 175 176 176 176
177 177 177 178 178 178 179 179
179 180 180 180 181 181 181 182
182 182 183 183 183 184 184 184
185 185 185 185 186 186 186 187
187 187 188 188 188 189 189 189
190 190 190 191 191 191 191 192
192 192 193 193 193 194 194 194
195 195 195 195 196 196 196 197
197 197 198 198 198 199 199 199
199 200 200 200 201 201 201 202
202 202 203 203 203 203 204 204
204 205 205 205 206 206 206 207
207 207 208 208 208 208 209 209
209 210 210 210 211 211 211 212
212 212 213 213 213 214 214 214
215 215 215 215 216 216 216 217
217 217 218 218 218 219 219 219
220 220 220 220 221 221 221 222
222 222 222 223 223 223 224 224
224 224 225 225 225 226 226 226
226 227 227 227 227 228 228 228
229 229 229 229 230 230 230 230
230 231 231 231 231 232 232 232
232 233 233 233 233 234 234 234
234 234 235 235 235 235 236 236
236 236 236 237 237 237 237 238
238 238 238 238 239 239 239 239
239 240 240 240 240 240 241 241
241 241 241 242 242 242 242 243
243 243 243 243 244 244 244 244
244 245 245 245 245 245 246 246
246 246 246 247 247 247 247 248
248 248 248 248 249 249 249 249
250 250 250 250 251 251 251 251
251 252 252 252 253 253 253 253
254 254 254 254 255 255 255 255 >;
};
};
};
};
backlight {
panel_a_wxga_8_0_bl: panel-a-wxga-8-0-bl {
status = "disabled";
compatible = "a,wxga-8-0-bl";
pwms = <&tegra_pwm 1 1000000>;
max-brightness = <255>;
default-brightness = <224>;
bl-measured = < 0 0 1 2 3 4 5 6
7 8 9 9 10 11 12 13
13 14 15 16 17 17 18 19
20 21 22 22 23 24 25 26
27 27 28 29 30 31 32 32
33 34 35 36 37 37 38 39
40 41 42 42 43 44 45 46
47 48 48 49 50 51 52 53
54 55 56 57 57 58 59 60
61 62 63 64 65 66 67 68
69 70 71 71 72 73 74 75
76 77 77 78 79 80 81 82
83 84 85 87 88 89 90 91
92 93 94 95 96 97 98 99
100 101 102 103 104 105 106 107
108 109 110 111 112 113 115 116
117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132
133 134 135 136 137 138 139 141
142 143 144 146 147 148 149 151
152 153 154 155 156 157 158 158
159 160 161 162 163 165 166 167
168 169 170 171 172 173 174 176
177 178 179 180 182 183 184 185
186 187 188 189 190 191 192 194
195 196 197 198 199 200 201 202
203 204 205 206 207 208 209 210
211 212 213 214 215 216 217 219
220 221 222 224 225 226 227 229
230 231 232 233 234 235 236 238
239 240 241 242 243 244 245 246
247 248 249 250 251 252 253 255 >;
};
};
};
I only changed the display settings and initialization commands
Check the driver code and dmesg. You shall find the driver code (dc.c) uner nvidia directory.
Modify the panel driver regulator to meet your hardware design.
Check this:
Are there any mistakes in this code?
dc@54240000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,fb-bpp = <32>;
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
nvidia,dc-or-node = "/host1x/dsi";
nvidia,dc-connector = <&dsi>;
/* DSI supplies */
avdd_dsi_csi-supply = <&max77620_sd3>;
avdd_lcd-supply = <&battery_reg>;
dvdd_lcd-supply = <&battery_reg>;
vdd_lcd_bl_en-supply = <&battery_reg>;
vdd_lcd_bl-supply = <&battery_reg>;
win-mask = <0x7>; /* Assign only wins A/B/C */
};
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = "okay";
nvidia,active-panel = <&panel_a_wxga_8_0>;
nvidia,dsi-csi-loopback;
panel-a-wxga-8-0 {
status = "okay";
/* Only 2 lanes used on Porg */
nvidia,dsi-n-data-lanes = <2>;
};
Can you give any more code examples on how to set up dsi for the display?
Read the post I just shared. There is documentation for the dsi device tree property meaning.
Hi @WayneWWW , great news as we are making some headway so thank you.
Here is the next concern of their progress. They are asking if there are more examples that can cover the additional concerns.
For now i am already initialized the mipi-dsi interface, and seams that the kernel attached the display to the dis interface. The next step, what i am doing now, it is initialization the display and turn on the backlight
It would be great, if they send any examples of the mipi display initialization
Specifically:
I would like to see information on how to init power the display, as well as in what format to send initialization commands. In examples of that posts, for it used the commands <TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE and <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM. I can`t find the description of the parameters
here is documentation that I have found.
Hi,
You could refer to the TX1 SoC TRM (technical reference manual) chapter 26: DISPLAY INTERFACES: MIPI-DSI
BTW, I am not quite sure about why you are asking me about what is DCS_LONG_WRITE and DCS_WRITE_1PARAM.
DSI_DCS_WRITE_1_PARAM should be short write with 1 parameter.
DCS_LONG_WRITE means long write.
They should be defined in the MIPI-DSI spec.
We have lots of kind of panel dts and even google search could find it.
For example, each of the dtsi file in below is for a specific kind of panel (some of them are eDP but not DSI).
Hi @WayneWWW
The engineer is having an issue connecting the PWM for the backlight. Here is his query.
Question. Is it enough to configure the PWM pin in pinmux, or do I need more PWM settings? And if so, in what part of the device tree?
Also, I found these posts but many of them don’t seem to resolve.
This is a thread that pertains to PWM that might be helpful. Please read through carefully as it’s a pretty long thread.
this one as well but alas it doesn’t seem to resolve and the issue seems pretty similar. is there a particular thread where this is resolved?
Me again; we moved the software stack to Jetson Nano 4g (compared to the earlier 2g), and the same problem emerged.
I did the full reflashing of the device to make sure that backlight pwm pin is assigned the appropriate function and settings.
In short, I see the following when I boot the device:
• devm 0x700031fc → 0x01
• devm 0x6000d504 → 0x02
Once I write:
devm 0x700031fc 8 0x45
I can run pwmchip0/pwm0 by hand and it works. How can I enforce this change to happen in device tree, and not manually?
Second part, when I put backlight-pwm driver on top of this pwm0_0, but it doesn’t work at all, with or without devm commands.
Any help is welcome.
Thanks in advance
here is another.
Hi,
Just to clarify because it seems too many info which is not helpful from your comment.
If you need to modify 0x700031fc to make things work, it means your pinmux setting is not correct from the beginning.
Please do not refer to any post from xavier or TX2 pinmux setting because the method for jetson nano is different. Jetson nano only uses dts to configure the pinmux. However, xavier/tx2 are using mb1 config file. Please check if you include the correct dtsi file generated from the pinmux spread sheet file to your kernel dts.
If I remember correctly, the backlight example that was validated on this SoC was on TX1. And there was a TI lp8557 backlight IC involved.
hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
→ lp8557-backlight-a-wuxga-8-0@2c
This will trigger the function call in kernel/kernel-4.9/drivers/video/backlight/lp855x_bl.c and devm_backlight_device_register.
The point here you need to implement the backlight driver by yourself.
Hi @WayneWWW ,
Thanks so much for all your help it’s super appreciated. A question I have about your latest post. When you say implement the backlight driver yourself is that a driver from the display manufacturer? Not an engineer question but for me I am trying to assure my bearings are straight.
Also, do you have a post or further reference to this information?
hardware/nvidia/platform/t210/jetson/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
→ lp8557-backlight-a-wuxga-8-0@2c
This will trigger the function call in kernel/kernel-4.9/drivers/video/backlight/lp855x_bl.c and devm_backlight_device_register.
thanks,
Christian
When you say implement the backlight driver yourself is that a driver from the display manufacturer?
I don’t know if there is any display vendor provided any existing driver code. What I am talking about here is we once implemented one because our board uses lp8557 TI.
And no, I don’t have any post for this info.
You can try to check the driver code and also the panel.c driver code in kernel source which is also under dc directory in kernel/nvidia.
Hi @WayneWWW,
I’m a little confused. Where does one get the backlight driver code come from? When you say check the driver code and or the panel.c driver code in kernel source would one expect to locate backlight driver code there?
If not, what are the details needed to manually install driver code there. I am assuming the engineers will understand what Ip8557 TI is but is there anything else about it when installing or “activating” driver code the engineers would need to install this?
Thanks,
Christian
Hi,
Basically, you could just think of the backlight driver and display driver are totally independent to each other.
The display driver could work even without the backlight (and of course you cannot see screen because no backlight).
And the backlight registration has its own driver. For example, you could refer to below link and see how those driver works in upstream code.
I am not asking you to install any driver. My point here is the engineer should refer to such code (as above link) and write your own driver.
In the end, there would be a node “backlight” generated in linux sysfs and you can adjust the pwm value there.
Honestly, this is almost same as what you are doing now through pwm node in sysfs.
If you don’t want to implement your own driver ,then use the pwm node to adjust the value is also okay…
For example, run a script to enable pwm node every time the device boots up.