Enable LVDS display using DSI/LVDS bridge converter on Jetson Nano Custom board

Hello,
In our custom board we are using Jetson Nano SOM and we want to interface LVDS display into DSI interface using DSI to LVDS bridge converter SN65DSI83.
I have referred to the following forum post and made changes to my kernel & dts and now sn65dsi83 bridge driver seems to be loaded successfully and no errors in its interrupt status regs (0xE5) but still I can’t see anything on the display, just white screen. what am missing here ?

DTSI

/ {
	host1x {

		/* DSI mapped to tegradc.1 */
		dc@54240000 {
			status = "okay";
			nvidia,dc-or-node = "/host1x/dsi";
			nvidia,dc-connector = <&dsi>;
			/* DSI supplies */
			avdd_dsi_csi-supply = <&max77620_sd3>;
			avdd_lcd-supply = <&battery_reg>;
			dvdd_lcd-supply = <&battery_reg>;
			vdd_lcd_bl_en-supply = <&battery_reg>;
			vdd_lcd_bl-supply = <&battery_reg>;
		};

		dsi {
			nvidia,dsi-controller-vs = <DSI_VS_1>;
			status = "okay";
			nvidia,active-panel = <&panel_dsi2lvds>;

			panel_dsi2lvds: panel_dsi2lvds {
				status = "okay";
				compatible = "c,wxga-14-0";
				nvidia,dsi-instance = <0>;
				nvidia,dsi-n-data-lanes = <2>;
				nvidia,dsi-pixel-format = <3>;		/* 24 bit planar*/
				nvidia,dsi-refresh-rate = <60>;
				nvidia,dsi-video-data-type = <0>; //TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE
				nvidia,dsi-video-clock-mode = <0>; //Continuous clock (1-tx)
				nvidia,dsi-video-burst-mode = <1>;
				nvidia,dsi-ganged-type = <0>;		/* 0= not used, 1=left/right, 2=odd/even 3=overlapped ?*/
				nvidia,dsi-split-link-type= <0>;	/* split link, 1=A/B) */
				nvidia,dsi-ganged-swap-links = <0>;
				nvidia,dsi-ganged-write-to-all-links = <0>;
				nvidia,dsi-controller-vs = <1>;
				nvidia,dsi-virtual-channel = <0>;
				nvidia,dsi-panel-reset = <1>;
				//nvidia,panel-bl-pwm-gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(V, 0) 1>; /* PV0 */
				nvidia,dsi-ulpm-not-support = <1>;
				nvidia,dsi-suspend-stop-stream-late = <1>;
				nvidia,dsi-power-saving-suspend = <1>;
				nvidia,default_color_space = <1>;

				pwms = <&tegra_pwm 0 40161>;

				disp-default-out {
					nvidia,out-type = <2>;
					nvidia,out-width = <216>;
					nvidia,out-height = <135>;
					nvidia,out-flags = <(0 << 3)>;
					nvidia,out-xres = <1280>;
					nvidia,out-yres = <800>;
				};
				display-timings {
					/delete-node/ 1200x1920-32-60Hz;  /* remove existing resolution */

					1280x800-32-60Hz {
						clock-frequency = <72000000>;
						hactive = <1280>;
						vactive = <800>;
						hfront-porch = <72>;
						hback-porch = <88>;
						vfront-porch = <15>;
						vback-porch = <23>;
						hsync-len = <13>;
						vsync-len = <2>;
						hsync-active = <0>;
						vsync-active = <0>;
						de-active = <1>;
						nvidia,h-ref-to-sync = <1>;
						nvidia,v-ref-to-sync = <11>;
					};
				};
			};
		};
	};
};

DTS:

	i2c@7000c000 {
		status = "okay";
		sn65dsi84_1: sn65dsi84@2c {
			status = "okay";
			compatible = "ti,sn65dsi83";
			reg = <0x2c>;
			ti,dsi-lanes = <2>;
			ti,lvds-format = <0>;
			ti,lvds-bpp = <24>;
			ti,width-mm = <216>;
			ti,height-mm = <135>;
			ti,lvds-channels = <1>;
			ti,always-on=<1>;
			ti,no-drm-connect=<1>;
			ti,reverse-lvds=<0>;
			
			dsi-lanes = <2>;
			panel-width-mm = <216>;
			panel-height-mm = <135>;
			

			display-timings {
				timing {
					clock-frequency = <72000000>;
					hactive = <1280>;
					vactive = <800>;
					hfront-porch = <72>;
					hback-porch = <88>;
					vfront-porch = <15>;
					vback-porch = <23>;
					hsync-len = <13>;
					vsync-len = <2>;
					hsync-active = <0>;
					vsync-active = <0>;
					de-active = <1>;
				};
			};

			port {
				panel1_in: endpoint {
					remote-endpoint = <&mipi_dsi_bridge_out>;
				};
			};
		};
	};


	mipi_dsi_bridge {
		status = "okay";
		clock-drop-level = <1>;
		port@1 {
			mipi_dsi_bridge_out: endpoint {
				remote-endpoint = <&panel_dsi2lvds>;
			};
		};

	};

Log:
dmesg_log.txt (10.3 KB)

After 5mins, I see ‘powerdown’ and also I see SN65DSI83’s 0xE5 register set from 0x0 to 0x1 (i.e PLL LOCK to UNLOCK) and I did ‘echo 0 > /sys/class/graphics/fb1/blank’, then again it got back to 0.(PLL LOCK)
Stil nothing seen in display.

Log:

[  309.619723] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x00
[  309.627644] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  326.186726] tegradc tegradc.1: blank - powerdown
[  331.122702] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x01
[  331.130431] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  352.626328] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x01
[  352.633878] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  374.129588] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x01
[  374.136800] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  391.645032] tegradc tegradc.1: unblank
[  391.645383] vdd_ds_1v8 regulator get failed
[  391.645399] lvds regulator get failed
[  391.677395] tegradc tegradc.1: nominal-pclk:1666000 parent:9995947 div:6.0 pclk:1665991 1649340~1815940
[  391.677986] tegradc tegradc.1: DSI: HS clock rate is 440000
[  395.633070] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x01
[  395.641061] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  417.137099] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x00
[  417.144639] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  438.640384] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x00
[  438.648466] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  460.145919] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x00
[  460.153251] sn65dsi83 0-002c: sn65dsi83_write: write reg 0xe5 data 0xff
[  481.648832] sn65dsi83 0-002c: sn65dsi83_read: read reg 0xe5 data 0x00

root@jetson-03:~# 
root@jetson-03:~# cat /dev/urandom > /dev/fb1
cat: write error: No such device
root@jetson-03:~# 
root@jetson-03:~# 

Kindly let me know if need more details. Thanks.
any insights would be helpful.

Hello,
Did you check the signals going into the display using an oscilloscope? The LVDS clock should be 72MHz and you should see ‘data’ on the LVDS data lanes that indicate there is pixel data. Also make sure the panel uses NI or Jeida data formatting.

What does the dmesg output say when the SN65DSI83 is initialised?

Regards,
Nico

Thanks for your response @nico4ocqz
I have already attached some portions (SN65DSI83 & tegra dc) of dmesg.
Attaching complete dmesg output logs here.
latest_dmesg.txt (59.9 KB)

The output looks good. I suggest checking the signals at the hardware side and whether the display is using NS or Jeida data formatting.

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