Hi all.
I’m currently trying to make the DSI output work on a custom TK1 board. I’m using a dsi2lvds bridge (sn65dsi84) which is connected on the DSI-0 output. The sn65dsi84 is properly set up and works fine and I can see the test video image from the chip. To output this test image you have to set both DSI and LVDS parameters and it needs the DSI clock, which is divided in order to create the LVDS clock. That means that the output clock from the DSI seems to be ok.
To make it work I’ve had to set the .dsi2lvds_bridge_enable = 1 in dsi_p_wuxga_10_1_pdata struct in arch/arm/mach-tegra/panel-p-wuxga-10-1.c. I’ve also force enable it in __tegra_dc_dsi_init() in drivers/video/tegra/dc/dsi.c
In dsi_p_wuxga_10_1_modes in arch/arm/mach-tegra/panel-p-wuxga-10-1.c, I’ve set the .pclk to 432000000, which is the 432MHz for the DSI clock. This clock drives the sn65dsi84 and I’ve programmed the divider to 1/6, so the LVDS clock ~72MHz. That seems to be working.
With my settings if I enable the test pattern in the sn65dsi84 with the command:
i2cset -y 1 0x2C 0x3C 0x10
I get the pattern.
When I’m probing with xrandr I get:
# xrandr
Screen 0: minimum 8 x 8, current 8 x 8, maximum 16384 x 16384
DSI-0 connected primary (normal left inverted right x axis y axis)
1920x1080 59.97 +
I don’t get any output in the screen though.
If I update the display settings, I get this message
xrandr -d :0 --output DSI-0 --mode 1920x1080
[ 1566.131724] tegradc tegradc.0: DSI: initializing panel p_wuxga_10_1
[ 1566.131838] p,wuxga-10-1 panel dt support not available
[ 1566.234193] tegradc tegradc.0: nominal-pclk:135666000 parent:406500000 div:3.0 pclk:135500000 134309340~147875940 type:2
[ 1566.290822] tegradc tegradc.0: DSI pad calibration done
[ 1566.344352] tegradc tegradc.0: dsi entered ULPM!
If you see there, for some reason the clock is set to 135MHz, although is set to 432MHZ in the driver.
Also during the kernel boot, I get this log
[ 1.322918] tegradc tegradc.0: DSI: HS clock rate is 407500
[ 1.323895] tegradc tegradc.0: DSI: initializing panel p_wuxga_10_1
[ 1.324222] p,wuxga-10-1 panel dt support not available
[ 1.426616] tegradc tegradc.0: nominal-pclk:432000000 parent:432000000 div:1.0 pclk:432000000 427680000~470880000 type:2
[ 1.515867] tegradc tegradc.0: DSI pad calibration done
[ 1.519821] tegradc tegradc.0: DSI: Enabling...
[ 2.125728] tegradc tegradc.0: DSI: Enabled
[ 2.128922] tegradc tegradc.0: dc.c probed
[ 2.129644] tegradc tegradc.0: nominal-pclk:135666000 parent:406500000 div:3.0 pclk:135500000 134309340~147875940 type:2
[ 2.151126] Console: switching to colour frame buffer device 240x67
[ 2.171460] tegradc tegradc.0: fb registered
Some debug prints are mine, so you’ll not find them in the source. Anyway, there it seems that the first time the correct clock is used, which is 432MHz and then in every tegra_dc_update_mode() which is called from drivers/video/tegra/dc/mode.c, a different clock is used. I haven’t set that clock. I don’t know from where it comes from. In the tegra_dc_program_mode() function which is called from tegra_dc_update_mode() to update the clocks, there is a terrifying comment which says
/* TODO: MIPI/CRT/HDMI clock cals */
This is right before the nominal-pclk and pclk is printed. Should I worry about that? Is that means that the drivers are incomplete?
The bottom line is that I can’t get the DSI work in the OS. Is there something I’m doing wrong? Am I missing something here?
Finally, this is the xorg.conf file I use.
# Copyright (c) 2011-2013 NVIDIA CORPORATION. All Rights Reserved.
#
# This is the minimal configuration necessary to use the Tegra driver.
# Please refer to the xorg.conf man page for more configuration
# options provided by the X server, including display-related options
# provided by RandR 1.2 and higher.
# Disable extensions not useful on Tegra.
Section "Module"
Disable "dri"
SubSection "extmod"
Option "omit xfree86-dga"
EndSubSection
EndSection
Section "Device"
Identifier "Tegra0"
Driver "nvidia"
Option "AllowEmptyInitialConfiguration" "true"
EndSection
Section "Monitor"
Identifier "DSI-0"
EndSection
Section "Monitor"
Identifier "HDMI-0"
Option "Ignore"
EndSection
Section "ServerLayout"
Identifier "Main Layout"
Screen 0 "Screen 1"
Screen 1 "Screen 2" RightOf "Screen 1"
Screen "Screen 3" Relative "Screen 1" 2048 0
EndSection
Section "Screen"
Identifier "Screen0"
Monitor "DSI-0"
Device "Tegra0"
EndSection
Section "Screen"
Identifier "Screen1"
Monitor "HDMI-0"
Device "Tegra0"
Option "Ignore"
SubSection "Display"
Modes "1920x1280"
EndSubSection
EndSection
Section "ServerLayout"
Identifier "X.org Configured"
Screen "Screen0"
EndSection
And this is me tegra_dsi_out struct
static struct tegra_dsi_out dsi_p_wuxga_10_1_pdata = {
.controller_vs = DSI_VS_1,
.dsi2lvds_bridge_enable = 1,
.n_data_lanes = 4,
.video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END,
.pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
.refresh_rate = 60,
.virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
.panel_reset = DSI_PANEL_RESET,
.power_saving_suspend = true,
.video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS, //TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
.dsi_init_cmd = dsi_p_wuxga_10_1_init_cmd,
.n_init_cmd = ARRAY_SIZE(dsi_p_wuxga_10_1_init_cmd),
.pkt_seq = panasonic_1920_1200_vnb_syne,
};
Thanks in advance!