Device tree DSI display init commands

Hi All,

In order to initialize my MIPI-DSI display I should provide it with init cmd in device tree.
But the docs contains very short description:

  • nvidia,dsi-init-cmd: panel required init command sequence.
  • nvidia,dsi-n-init-cmd: command counts of init command sequence, including delay set.

In the sample below you can find:

nvidia,dsi-init-cmd = <0x0 0x15 0x01 0x0 0x0>,
						      <1 20>,
						      <0x0 0x15 0xae 0x0b 0x0>,
						      <0x0 0x15 0xee 0xea 0x0>,
						      <0x0 0x15 0xef 0x5f 0x0>,
						      <0x0 0x15 0xf2 0x68 0x0>,
						      <0x0 0x15 0xee 0x0 0x0>,
						      <0x0 0x15 0xef 0x0 0x0>;
				nvidia,dsi-n-init-cmd = <8>;

As far I understand every 3rd byte is address, 4th byte is data.
But I cannot understand a meaning of <0x0 0x15 and 0x0>.
The second row is completely different…

In the datasheet for my display I found the next sequence:

Item	Addr 	P0
1	0xFE	0x08
2	0x03	0x40
3	0x07	0x1A
4	0xFE	0x00
5	0x51	0xFF

I would appreciate any help and explanations.

Hello,
Can you refer to DTS source, like arch/arm/boot/dts/panel-s-wqxga-10-1.dtsi?
the command should like the following:

nvidia,dsi-init-cmd =
/* Long  Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
/* For DSI packets each DT cell is interpreted as u8 not u32 */

<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0x10 0x00 0x2A 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0x10 0x01 0x01 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_NO_OP 0x0 0x0>,

Those definitions of constants can be found in kernel source.

br
ChenJian

Thank you for your comment.

Certainly, I have seen the examples you specified.

As far I understand looking at the datasheet my display requires only short packets during init sequence. But could you clarify a difference and cases for using DSI_DCS_WRITE_0_PARAM and DSI_DCS_WRITE_1_PARAM flags?

Finally, I have found a solution.

Hi Alex,

Would you please help me to interface 10.1" MIPI 4 Lane AUO 1920x1200 LCD to Jetson TK1?
I am facing kernel driver issue.

Thanks,

TD

Hi TulgaD,

Which kind of problem you found? Could you explain?

I actually tried to connect AUO MIPI SDI to TX1, but not TK1.
Hope, it should be similar.
I’m not sure that I can go deep into your development, but I will answer for obvious for me questions indeed.

Best regards,
Alex

Hi Alex,

Problem is that i do not see any picture on the screen because we can’t initiate mipi driver on the kernel. It seems mipi driver implementation is not well settled in TK1. However, would you please provide me steps how you initiated mipi driver on TX1?
For example, did you only configure DTS file as you mentioned above? What else did you do?

Thanks a lot,

TD

Hi TulgaD,

There are at least two issues on the way to make MIPI DSI panel work.

  1. Choose or write appropriate driver.
  2. Provide driver with appropriate init sequence writing DT records.

The driver code is mostly about physical requirements, for example power sequencing. But also it can limit access to some advanced features or modes, for example 8-lane mode.

The most tricky thing is writing an init sequence just because most of manufacturers have unclear description of this part of the device.

Which panel driver you are using at the moment? Your own or from L4T?

Did you find a clear description of the init sequence in your datasheet?

To provide you with more info I should know:

  • circuit diagram how exactly your display is connected
  • datasheet
  • name of driver you are trying to use
  • kernel config
  • source of the device tree

Again, I cannot promise a good support, but can look and point your attention on some important thins…

Best regards,
Alex

Hi Alex,

Thanks for the detailed description.

I am using panel driver “panel-p-wuxga-10-1.c” and it is included in the kernel itself. It is from L4T. I did not do anything in this file.

In the datasheet, there are not clear but initiating information. I do not clearly understand it.

Here, I attached picture of the circuit diagram for LCD connection to the CPU.

Name of the driver is: panel-p-wuxga-10-1.c
LCD Device is: B101UAN01.7_H/W 1A Datasheet link: http://www.yslcd.com.tw/docs/product/B101UAN01.7.pdf

Kernel config:

...
CONFIG_TEGRA_GRHOST=y
CONFIG_TEGRA_DC=y
CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT=y
CONFIG_TEGRA_DSI=y
CONFIG_TEGRA_DSI2EDP_SN65DSI86=y
CONFIG_TEGRA_DP=y
CONFIG_TEGRA_NVSR=y
CONFIG_TEGRA_NVHDCP=y
...

Name of Device Tree: tegra124-jetson_tk1-pm375-000-c00-00.dts

Source of Device Tree:

host1x {
		dsi {
		compatible = "nvidia,tegra124-dsi";
			reg = <0x54300000 0x00040000>,
			      <0x54400000 0x00040000>;
			status = "okay";
			nvidia,dsi-controller-vs = <1>;
			panel-l-wxga-7 {
				status = "okay";
				compatible = "lg,wxga-7";
				nvidia,dsi-instance = <0>;
				nvidia,dsi-n-data-lanes = <4>;
				nvidia,dsi-pixel-format = <3>;
				nvidia,dsi-refresh-rate = <60>;
				nvidia,dsi-video-data-type = <0>;
				nvidia,dsi-video-clock-mode = <0>;
				nvidia,dsi-video-burst-mode = <0>;
				nvidia,dsi-virtual-channel = <0>;
				nvidia,dsi-power-saving-suspend = <1>;
				nvidia,dsi-phy-datzero = <270>;
				nvidia,dsi-phy-hsprepare = <30>;
				nvidia,dsi-phy-clkzero = <330>;
				nvidia,dsi-phy-clkprepare = <27>;
				nvidia,dsi-init-cmd = <0x0 0x15 0x01 0x0 0x0>,
						      <1 20>,
						      <0x0 0x15 0xae 0x0b 0x0>,
						      <0x0 0x15 0xee 0xea 0x0>,
						      <0x0 0x15 0xef 0x5f 0x0>,
						      <0x0 0x15 0xf2 0x68 0x0>,
						      <0x0 0x15 0xee 0x0 0x0>,
						      <0x0 0x15 0xef 0x0 0x0>;
				nvidia,dsi-n-init-cmd = <8>;
				nvidia,dsi-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>,
							 <1 160>;
				nvidia,dsi-n-suspend-cmd = <2>;
				nvidia,dsi-late-resume-cmd = <0x0 0x15 0x10 0x0 0x0>,
							     <1 120>;
				nvidia,dsi-n-late-resume-cmd = <2>;
				nvidia,dsi-early-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>,
							       <1 160>;
				nvidia,dsi-n-early-suspend-cmd = <2>;
			};
		};
	};

It is ok Alex, I will greatly appreciated if you point out important things.

Thanks,

TD

Hi TulgaD,

I assume that all about electrical connection and power sequencing are OK.

I feel that panel-a drivers may be more suitable for your case.

Taking written above aside as far I see right here taking into account my TX1 experience:

  1. You need to turn on dc@54200000 turned off by default to make DSI work.
/ {

        host1x {
                dc@54200000 {
                        status = "okay";
                };
                dsi {
                        status = "okay";
...
  1. Make sure that your compatible
string compatible = "lg,wxga-7";

is matched with appropriate one in driver code.
In my version of kernel it should be p,wuxga-10-1

  1. Your DT does not have resolution description, timings and backlight.

My version of DT for another AOU DSI panels uses panel-a-1200-1920-8-0.c and looks like this:

/*
 * arch/arm/boot/dts/panel-a-wuxga-7-0-aou.dtsi
 *
 * Copyright (c) 2016, Artec Europe Sarl.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <dt-bindings/display/tegra-dc.h>
#include <dt-bindings/display/tegra-panel.h>

/ {

	host1x {
		dc@54200000 {
			status = "okay";
		};
		dsi {
			status = "okay";
			nvidia,dsi-controller-vs = <DSI_VS_1>;
			panel-a-wuxga-7-0 {
				status = "okay";
				compatible = "a,wuxga-8-0";
				nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
				nvidia,dsi-dpd-pads = <DSIC_DPD_EN DSID_DPD_EN>;
				nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 2) 0>; /* PV2 */
				nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0>; /* PV0 */
				nvidia,dsi-instance = <DSI_INSTANCE_0>;
				nvidia,dsi-n-data-lanes = <4>;
				nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
				nvidia,dsi-refresh-rate = <60>;
				nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
				nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
				nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
				nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
				nvidia,dsi-lp00-pre-panel-wakeup = <TEGRA_DSI_ENABLE>;

				nvidia,dsi-init-cmd = <1 250>,
						      <0x0 0x15 0xfe 0x08 0x0>,
						      <0x0 0x15 0x03 0x40 0x0>,
						      <0x0 0x15 0x07 0x1a 0x0>,
						      <0x0 0x15 0xfe 0x00 0x0>,
						      <0x0 0x15 0x51 0xff 0x0>,
						      <TEGRA_DSI_DELAY_MS 20>,
						      <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
						      <TEGRA_DSI_DELAY_MS 200>,
						      <TEGRA_DSI_SEND_FRAME 1>,
						      <TEGRA_DSI_DELAY_MS 20>,
						      <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
						      <TEGRA_DSI_DELAY_MS 120>;
				nvidia,dsi-n-init-cmd = <13>;
				disp-default-out {
					nvidia,out-type = <TEGRA_DC_OUT_DSI>;
					nvidia,out-width = <68>;
					nvidia,out-height = <121>;
					nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
					nvidia,out-parent-clk = "pll_d_out0";
					nvidia,out-xres = <1080>;
					nvidia,out-yres = <1920>;
				};
				display-timings {
					1080x1920-32 {
						clock-frequency = <131569920>;
						hactive = <1080>;
						vactive = <1920>;
						hfront-porch = <32>;
						hback-porch = <11>;
						hsync-len = <5>;
						vfront-porch = <12>;
						vback-porch = <7>;
						vsync-len = <5>;
						nvidia,h-ref-to-sync = <1>;
						nvidia,v-ref-to-sync = <1>;
					};
				};
			};
		};
	};

It is important to have display-timings section.
My sample is AMOLED and does not have a backlight, but yours has.

  1. Your datasheed does not have DSI registers init sequence, but DT has. Perhaps it is not right.
    Actually you have to ask manufacturer to clarify the DSI init sequence.

  2. I see first time a DSI panel without init sequence, but with I2C EDID. The drivers from the L4T does not have a I2C EDID support. Moreover, all the described registers are I2C ones. But there is nothing about DSI registers. So, datasheet is most strange I’ve ever seen.

Hope it helps.

Alex

Hi Alex,

Thanks a lot, I will try to initiate this DSI interface as per your advise. I will let you know the result.

Thanks,

TD

Be aware, my init sequence is from my panel’s datasheet, you might be different.

Alex,

Can you tell what is your panel version? If it is possible, please send me the datasheet? I just want to compare it.

Thanks,

TD

Sorry TD, I have a special model and cannot disclose the datasheet.
Please believe me, in your datasheet the whole section about MIPI registers, commands, state switching and init sequence is missing.

Alex,

Thanks for the reply. I contacted with the manufacturer they said that this LCD does not need any MIPI registers, commands, state switching and init sequence.

What if there is no need mipi registers and etc, what is wrong with the code can you quickly look at it?
Its clock frequency is 148.35MHZ.

And there is another question what is DE Mode?

Thanks,

TD

I see first time such type of display. It looks like a hybrid. Perhaps it is an old fashion panel equipped MIPI to LVDS bridge or something like that.

You are right. According the datasheet a clock rate is 148.35MHz.

I have no idea about DE Mode in terms of DSI.
DE Mode means working without real HSync/VSync, but normally DSI uses it…

So, in fact you have some extraordinary case.

Good luck,
Alex

Hi Chejian,

Can you help me on DSI Driver on Tegra K1? I have tried to integrate AUO MIPI LCD B101UAN01.7 into our customized system based on TEGRA K1 CPU. So far we have checked everything around connection to CPU and its schematics. It seems everything is correct. For the LCD, it has ORISE TECH OCT3108B-HV161 MIPI IC and it is different than usual MIPI LCDs. However, I have contacted with the technical team of AUO and they said this lcd passive type of MIPI LCD. There is no need of initiating code and special sequence. I have enabled TK1 DSI configuration on kernel and changed the values in many different ways according to the Technical Reference Manual of TK1. There is no success at all.

I hope that you can tell us what we do wrong.

Thanks,

TD

Hi Alex,

How did you set the DSI is primary since HDMI is primary display? How did you activate DSI source? I think that configuration is correct on kernel level. In my opinion, I can’t switch between hdmi and dsi screens.

Thanks,

TD

Hi TD,

Since DSI is declared in DT it becomes a primary display.
It is no problem to use both. You just need to specify the display in xorg.conf or in uboot script to override defaults.

Best regards,
Alex

Hi Alex,

Can you describe a bit of U-Boot script to select?

Tnx

TD