DSI initialization

Hi, I’m trying to switch from HDMI to DSI display on a custom board. Pinout is compatible with P3448-0002 / b00.
I’ve followed advises from this and this topics. I’ve added new panel-.dtsi, panel-.c and modified teggra210-*-b00.dts, board-panel.h, board_panel.c of_dc.c and Makefiles so that everything is set up.
I’ve added some debug output to dc.c and dsi.c and everything seems OK. But I still have only black screen.
Display power and backlight are external, so I don’t manage them. The only thing I’m using except for DSI PHY is DSI reset on Pin206.

The problem might be in initialization sequence need to set all lanes in LP-11. But I can’t see any obvious way to do this. There is a line in dsi.c, that mentions LP-00

if (dsi->info.lp00_pre_panel_wakeup) {
tegra_dsi_pad_disable(dsi);
}

tegra_dsi_pad_disable seems to pull all lanes down
I’ve tried to use tegra_dsi_pad_enable before resetting the board, but it does’t work.
dsi_regs.h has macros for pulling down lanes, but not for pulling up.
Is there any way to set LP-11 on all lanes? Or is there any documentation on low-level DSI driver?

20201225.dmesg (75.4 KB)
panel-orustech-com50h5n03ulc.c (2.7 KB)
panel-orustech-com50h5n03ulc.dtsi (3.3 KB)
tegra210-p3448-0002-p3449-0000-b00.dts (1.9 KB)

Hey, @mrstecklo!

Can you share with me the display model you intend to use as well as the MIPI DSI connector pinout?

Thanks in advance!
Bojan.

Hi, @bojankoce
Here is display data sheet
com50h5n03ulc.pdf (790.5 KB)

There is also this document, that says how no enable two-lane mode
Dx5N03_MIPI_2Lane_mode_APN_20181031.pdf (51.6 KB)
And this one with the minimal init-sequence
D5N03_HD_MIPI-DSI_Checklist(HX8394-A11)_V1.xls (1.5 MB)

Could you also remove “nvidia,dsi-csi-loopback”?

That doesn’t help

I’ve also noticed that after init-sequence it switches clock LP->HS->LP->HS. Wonder if that means something

dmesg

dmesg | grep tegradc.1
[ 0.586832] iommu: Adding device tegradc.1 to group 14
[ 0.586927] platform tegradc.1: domain=ffffffc0f8f73258 allocates as[0]=ffffffc0f8e182b0
[ 0.588508] platform tegradc.1: IOVA linear map 0x0000000092cb0000(140000)
[ 0.588898] platform tegradc.1: IOVA linear map 0x00000000d7000000(19000000)
[ 1.467279] tegradc tegradc.1: disp1 connected to head1->/host1x/dsi
[ 1.467595] tegradc tegradc.1: No hpd-gpio in DT
[ 1.467617] tegradc tegradc.1: parse_disp_default_out: No parent clk. Using default clk
[ 1.467689] tegradc tegradc.1: DT parsed successfully
[ 1.467760] tegradc tegradc.1: Display dc.ffffff800d500000 registered with id=1
[ 1.469110] tegradc tegradc.1: prod settings missing -19
[ 1.469246] tegradc tegradc.1: tegra_dc_dsi_cp_info tegra_dc_dsi_cp_p_cmd
[ 1.469607] tegradc tegradc.1: tegra_dsi_init_sw
[ 1.470016] tegradc tegradc.1: pad_ab_default not found -19
[ 1.470022] tegradc tegradc.1: pad_ab_idle not found -19
[ 1.470026] tegradc tegradc.1: pad_cd_default not found -19
[ 1.470031] tegradc tegradc.1: pad_cd_idle not found -19
[ 1.473219] tegradc tegradc.1: probed
[ 1.474048] tegradc tegradc.1: fb registered
[ 1.474075] tegradc tegradc.1: _tegra_dc_controller_enable
[ 1.474090] tegradc tegradc.1: _tegra_dc_controller_enable enable
[ 1.474096] tegradc tegradc.1: dsi_com50h5n03ulc_enable
[ 1.480259] tegradc tegradc.1: dsi_com50h5n03ulc rst pin: 168
[ 1.486940] tegradc tegradc.1: nominal-pclk:28940000 parent:28939746 div:1.0 pclk:28939746 28650600~31544600
[ 1.487031] tegradc tegradc.1: _tegra_dc_controller_enable ops enable
[ 1.487038] tegradc tegradc.1: tegra_dc_dsi_enable
[ 1.487570] tegradc tegradc.1: dsi->enabled == false
[ 1.487576] tegradc tegradc.1: tegra_dsi_init_hw
[ 1.487583] tegradc tegradc.1: tegra_dsi_init_clock_param
[ 1.487590] tegradc tegradc.1: h_width = 896, v_width = 1292, refresh = 24999
[ 1.487594] tegradc tegradc.1: refresh rate = 25
[ 1.487601] tegradc tegradc.1: pixel clk = 28940800 Hz
[ 1.487606] tegradc tegradc.1: byte_clk = (28940800 * 3) / (1 * 2) = 43411200 Hz
[ 1.487612] tegradc tegradc.1: DSI: HS clock rate is 174000
[ 1.487617] tegradc tegradc.1: tegra_dsi_set_dsi_clk(10000)
[ 1.487621] tegradc tegradc.1: pixel clock = 1666 kHz
[ 1.490686] tegradc tegradc.1: bit clock = 50025 ps
[ 1.494235] tegradc tegradc.1: tegra_dsi_pad_calibration
[ 1.494240] tegradc tegradc.1: tegra_dsi_pad_enable
[ 1.495532] tegradc tegradc.1: dsi->ulpm == false
[ 1.495538] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 1.495544] tegradc tegradc.1: tegra_dsi_set_dsi_clk(10000)
[ 1.495549] tegradc tegradc.1: pixel clock = 1666 kHz
[ 1.498573] tegradc tegradc.1: bit clock = 50025 ps
[ 1.498588] tegradc tegradc.1: tegra_dsi_pad_disable
[ 1.498691] tegradc tegradc.1: _tegra_dc_controller_enable postpoweron
[ 1.498697] tegradc tegradc.1: dsi_com50h5n03ulc_postpoweron
[ 1.603436] tegradc tegradc.1: reset 0
[ 1.715470] tegradc tegradc.1: reset 1
[ 1.927431] tegradc tegradc.1: _tegra_dc_controller_enable ops postpoweron
[ 1.927435] tegradc tegradc.1: tegra_dc_dsi_postpoweron
[ 1.927439] tegradc tegradc.1: tegra_dc_dsi_postpoweron sending dsi init cmd
[ 1.958006] tegradc tegradc.1: tegra_dsi_prepare_host_transmission
[ 1.958018] tegradc tegradc.1: dsi->status.lphs != DSI_LPHS_NOT_INIT
[ 1.958028] tegradc tegradc.1: _tegra_dsi_controller_write_data
[ 1.959197] tegradc tegradc.1: tegra_dsi_restore_state
[ 1.959200] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 1.959205] tegradc tegradc.1: tegra_dsi_prepare_host_transmission
[ 1.959215] tegradc tegradc.1: dsi->status.lphs != DSI_LPHS_NOT_INIT
[ 1.959224] tegradc tegradc.1: _tegra_dsi_controller_write_data
[ 1.960630] tegradc tegradc.1: tegra_dsi_restore_state
[ 1.960633] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 1.960638] tegradc tegradc.1: tegra_dsi_prepare_host_transmission
[ 1.960649] tegradc tegradc.1: dsi->status.lphs != DSI_LPHS_NOT_INIT
[ 1.960655] tegradc tegradc.1: _tegra_dsi_controller_write_data
[ 1.962013] tegradc tegradc.1: tegra_dsi_restore_state
[ 1.962016] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 1.962020] tegradc tegradc.1: tegra_dsi_prepare_host_transmission
[ 1.962030] tegradc tegradc.1: dsi->status.lphs != DSI_LPHS_NOT_INIT
[ 1.962036] tegradc tegradc.1: _tegra_dsi_controller_write_data
[ 1.963155] tegradc tegradc.1: tegra_dsi_restore_state
[ 1.963158] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 1.963162] tegradc tegradc.1: tegra_dsi_prepare_host_transmission
[ 1.963172] tegradc tegradc.1: dsi->status.lphs != DSI_LPHS_NOT_INIT
[ 1.963178] tegradc tegradc.1: _tegra_dsi_controller_write_data
[ 2.163312] tegradc tegradc.1: tegra_dsi_restore_state
[ 2.163315] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 2.163320] tegradc tegradc.1: tegra_dsi_prepare_host_transmission
[ 2.163330] tegradc tegradc.1: dsi->status.lphs != DSI_LPHS_NOT_INIT
[ 2.163337] tegradc tegradc.1: _tegra_dsi_controller_write_data
[ 2.213464] tegradc tegradc.1: tegra_dsi_restore_state
[ 2.213467] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 2.213471] tegradc tegradc.1: tegra_dsi_send_dc_frames
[ 2.213474] tegradc tegradc.1: tegra_dsi_set_to_hs_mode
[ 2.213479] tegradc tegradc.1: tegra_dsi_set_dsi_clk(174000)
[ 2.213482] tegradc tegradc.1: pixel clock = 29000 kHz
[ 2.216534] tegradc tegradc.1: bit clock = 2874 ps
[ 2.216564] tegradc tegradc.1: tegra_dsi_start_dc_stream
[ 2.416935] tegradc tegradc.1: tegra_dsi_set_to_lp_mode
[ 2.417540] tegradc tegradc.1: tegra_dsi_set_dsi_clk(10000)
[ 2.417543] tegradc tegradc.1: pixel clock = 1666 kHz
[ 2.420587] tegradc tegradc.1: bit clock = 50025 ps
[ 2.420599] tegradc tegradc.1: tegra_dsi_set_to_hs_mode
[ 2.420602] tegradc tegradc.1: tegra_dsi_set_dsi_clk(174000)
[ 2.420605] tegradc tegradc.1: pixel clock = 29000 kHz
[ 2.423647] tegradc tegradc.1: bit clock = 2874 ps
[ 2.423676] tegradc tegradc.1: tegra_dsi_start_dc_stream
[ 7.494526] tegradc tegradc.1: unblank

I’ve found documentation on low-level DSI driver in Tegra X1 TRM.
Seems like driver is not capable of explicitly entering STOP/LP-11 state.
STOP state is only mentioned in context of ULPM

Problem solved. It was PCB issue.
LP-11 is the default state if no data is transferred.

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