Using a Jetson Nano 4G module on a custom board with 1920 x RGB(3) x 1200 MIPI DSI (Video Mode Only) display. The display backlight turns on when booting and stays on. The display is always blank. When dumping the registers it reports “DSI controller suspended”. And lots of warnings print when trying to disable blank. The dmesg shows “tegradc tegradc.0: blank - powerdown” over and over again. See below for logs and device tree. During boot up DSI_D1 pins toggle for a short time, but do not toggle after boot up. How can I get something to show on the display?
It also seems the “pll_d_out0” req_rate doesn’t match the actual rate in the clk_summary.
rate = 9995947
req_rate = 163200000
But in the boot log pclk seems to match the device tree and is in the required range of the display.
[ 1.428886] tegradc tegradc.0: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
Yes, I’m using a nano 4gb module with sdcard slot on a custom board.
Doing the command “echo 0 > /sys/class/graphics/fb0/blank” several times caused it to eventually exit suspend mode. Attached is the log. The “panel_sanity” has many warnings, but reported “Sanity check successful”. But “read_panel” reported incorrect “max reg payload size” of zero. Seems it is not correctly talking to the panel. The nano regs dump is also in the log.
Thank you for your recommendation to use the Jetson Nano 4G module with eMMC (B01). After receiving the new module with eMMC, we get similar results. The backlight works, but the display does not work. The new log file, reg file, and device tree files are attached. Any help would be appreciated.
For the pll_d_out0 clock rate difference mentioned, could you also share the clock tree?
And also, would be helpful if you can look into the dsi clock programming details in dsi.c to check why the final value is not correct for pll_d_out0. Looks like the value printed for pixel_clock is correct though.
I don’t think either the first or the second is correct. When the requested pixel clock is 148,500,000, I get the below. The clk_summary seems to indicate a desired pll_d_out0 of 163,200,000, but an actual rate of 750,000,000 or 9,995,947. Also, 163,200,000 doesn’t match the desired pixel clock rate of 148,500,000.
from the device tree:
nvidia,out-parent-clk = “pll_d_out0”;
clock-frequency = <148500000>;