Enable SPI1 as Slave on Jetson Orin NX

[graceagrace]

Hi there,

I am trying to use SPI1 in slave mode, but am having issues that other similar forum posts have not helped me resolve.

Steps I took to enable SPI1 as a slave are as follows:

• Modify the device tree to reference the slave driver. The full entry in my device tree looks like this:

spi@3210000 {
	compatible = "nvidia,tegra186-spi-slave";
	reg = <0x00 0x3210000 0x00 0x10000>;
	interrupts = <0x00 0x24 0x04>;
	#address-cells = <0x01>;
	#size-cells = <0x00>;
	iommus = <0x06 0x04>;
	dma-coherent;
	dmas = <0x3f 0x0f 0x3f 0x0f>;
	dma-names = "rx\0tx";
	spi-max-frequency = <0x3dfd240>;
	nvidia,clk-parents = "pll_p\0clk_m";
	clocks = <0x02 0x87 0x02 0x66 0x02 0x0e>;
	clock-names = "spi\0pll_p\0clk_m";
	resets = <0x02 0x5b>;
	reset-names = "spi";
	status = "okay";
	phandle = <0x312>;

	prod-settings {
		#prod-cells = <0x04>;

		prod {
			prod = <0x00 0x194 0x80000000 0x00>;
		};
	};

	spi@0 {
		compatible = "tegra-spidev";
		reg = <0x00>;
		spi-max-frequency = <0x2faf080>;

		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,cs-setup-clk-count = <0x20>;
			nvidia,rx-clk-tap-delay = <0x10>;
			nvidia,tx-clk-tap-delay = <0x0f>;
		};
	};

	spi@1 {
		compatible = "tegra-spidev";
		reg = <0x01>;
		spi-max-frequency = <0x2faf080>;

		controller-data {
			nvidia,rx-clk-tap-delay = <0x10>;
			nvidia,tx-clk-tap-delay = <0x0f>;
		};
	};
};

• Change the pinmux to enable SPI as a slave, as follows:

spi1_sck_pz3 {
	nvidia,pins = "spi1_sck_pz3";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

spi1_miso_pz4 {
	nvidia,pins = "spi1_miso_pz4";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

spi1_mosi_pz5 {
	nvidia,pins = "spi1_mosi_pz5";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

spi1_cs0_pz6 {
	nvidia,pins = "spi1_cs0_pz6";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

spi1_cs1_pz7 {
	nvidia,pins = "spi1_cs1_pz7";
	nvidia,function = "spi1";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_DISABLE>;
	nvidia,enable-input = <TEGRA_PIN_DISABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

I have attempted to verify SPI functionality by the methods mentioned in other posts (reading data with spidev_test or running a test Python script to read from the SPI device) without success.
Using the version of spidev_test provided by Nvidia in this forum post, I run this command:

./spidev_test -D /dev/spidev0.0 -s1500000 -g4 -b8 -p0 -n1 -r -zzz

And then try to read (4) bytes of data sent by the MCU master.
After running this command without success, when I read the kernel ring buffer, I see the following errors:

$ dmesg | grep spi
[    2.188445] spi-tegra124-slave 3210000.spi: Adding to iommu group 0
[    2.193789] spi-tegra124-slave 3210000.spi: Reset control is not found
[    9.306532] spi-tegra114 3230000.spi: Adding to iommu group 0
[  131.621011] spi-tegra124-slave 3210000.spi: waiting for controller was interrupted
[  131.621306] spi_master spi0: failed to transfer one message from queue

Are there any obvious issues with my configuration? I am unsure what the source of the “reset control is not found” error could be…

[graceagrace]

Further investigation on our end revealed this was a hardware problem on our custom carrier board. We are able to receive data as a SPI slave, now. This issue can be closed, but I hope the above configuration may serve as a helpful reference to others.