Enable SPI0

Hi,

I’m trying to enable SPI on the Jetson Xavier NX production module but I cant get it to work. I created a dtb overlay to enable it in the device tree and change the max clock speed (there are more unrelated changed in the complete overlay):

    fragment@4 {
        target-path = "/spi@3210000/spi@0";
        __overlay__ {
            spi-max-frequency = <10000000>;
        };
    };
    fragment@5 {
        target-path = "/spi@3210000/spi@1";
        __overlay__ {
            spi-max-frequency = <10000000>;
        };
    };
    fragment@6 {
        target-path = "/spi@3230000/spi@0";
        __overlay__ {
            spi-max-frequency = <10000000>;
        };
    };
    fragment@7 {
        target-path = "/spi@3230000/spi@1";
        __overlay__ {
            spi-max-frequency = <10000000>;
        };
    };
    fragment@8 {
        target = <&spi0>;
        __overlay__ {
            status = "okay";
        };
    };
    fragment@9 {
        target = <&spi2>;
        __overlay__ {
            status = "okay";
        };
    };

Later I also added the 40 pin header IO config to the overlay:


fragment@10 {
        target = <&pinmux>;
        __overlay__ {
            pinctrl-names = "default";
            pinctrl-0 = <&hdr40_pinmux>;
            hdr40_pinmux: header-40pin-pinmux {
                pin19 {
                    nvidia,pins = "spi1_mosi_pz5";
                    nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                    nvidia,tristate = <TEGRA_PIN_DISABLE>;
                    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };
                pin21 {
                    nvidia,pins = "spi1_miso_pz4";
                    nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                    nvidia,tristate = <TEGRA_PIN_DISABLE>;
                    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };
                pin22 {
                    nvidia,pins = "spi3_miso_py1";
                    nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                    nvidia,tristate = <TEGRA_PIN_DISABLE>;
                    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };
                pin23 {
                    nvidia,pins = "spi1_sck_pz3";
                    nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                    nvidia,tristate = <TEGRA_PIN_DISABLE>;
                    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };
                pin24 {
                    nvidia,pins = "spi1_cs0_pz6";
                    nvidia,pull = <TEGRA_PIN_PULL_UP>;
                    nvidia,tristate = <TEGRA_PIN_DISABLE>;
                    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };
                pin26 {
                    nvidia,pins = "spi1_cs1_pz7";
                    nvidia,pull = <TEGRA_PIN_PULL_UP>;
                    nvidia,tristate = <TEGRA_PIN_DISABLE>;
                    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };
            };
        };
    };

I also changed the pinmux config:

$ grep spi1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 0 Reg: 0x0243d010 Val: 0x00000458 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000454 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000454 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000458 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000454 -> spi1_mosi_pz5

To test I placed the board in a devkit carrier board and connected the probe to pin 23, and then sent some data to the SPI using:

$ echo -ne "\xFE" | spi-pipe -d /dev/spidev0.0 -s 1000000 | hexdump
0000000 0000
0000001

However there is no signal from the device. What I do find odd is that hexdump outputs data, which makes me think its still configured as loopback. Am I missing something obvious?

Please let me know if you need anymore info.

Rens

Have you try jetson-io to configure the pin? Below is my configure.

Bank: 0 Reg: 0x0243d010 Val: 0x00000448 → spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 → spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 → spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 → spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 → spi1_mosi_pz5

I run the board with a custom image build using yocto, so unfortunately I cannot use the jetson-io script. I will try your configuration to see if that makes it work.

Is there a resource available that explains the hex value as pinmux functions?

Add below header-40pin-pinmux to your dts.

	pinmux@2430000 {
		pinctrl-0 = <0x179>;
		pinctrl-names = "default";
		compatible = "nvidia,tegra194-pinmux";
		reg = <0x0 0x2430000 0x0 0x17000 0x0 0xc300000 0x0 0x4000>;
		#gpio-range-cells = <0x3>;
		status = "okay";
		linux,phandle = <0xab>;
		phandle = <0xab>;

		header-40pin-pinmux {
			phandle = <0x179>;
			linux,phandle = <0x179>;

			pin37 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi3_mosi_py2";
				nvidia,function = "spi3";
			};

			pin28 {
				nvidia,lpdr = <0x1>;
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen2_i2c_scl_pcc7";
				nvidia,function = "i2c2";
			};

			pin27 {
				nvidia,lpdr = <0x1>;
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen2_i2c_sda_pdd0";
				nvidia,function = "i2c2";
			};

			pin26 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi1_cs1_pz7";
				nvidia,function = "spi1";
			};

			pin24 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi1_cs0_pz6";
				nvidia,function = "spi1";
			};

			pin23 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_sck_pz3";
				nvidia,function = "spi1";
			};

			pin22 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi3_miso_py1";
				nvidia,function = "spi3";
			};

			pin21 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_miso_pz4";
				nvidia,function = "spi1";
			};

			pin19 {
				nvidia,lpdr = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_mosi_pz5";
				nvidia,function = "spi1";
			};

			pin18 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi3_cs0_py3";
				nvidia,function = "spi3";
			};

			pin16 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi3_cs1_py4";
				nvidia,function = "spi3";
			};

			pin13 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi3_sck_py0";
				nvidia,function = "spi3";
			};

			pin10 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x1>;
				nvidia,pull = <0x2>;
				nvidia,pins = "uart1_rx_pr3";
				nvidia,function = "uarta";
			};

			pin8 {
				nvidia,lpdr = <0x0>;
				nvidia,io-high-voltage = <0x0>;
				nvidia,enable-input = <0x0>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "uart1_tx_pr2";
				nvidia,function = "uarta";
			};
		};

I found what the problem was, a faulty channel on the oscilloscope. Apparently the trigger is broken.

In the end I did not have to adjust the PIN header in the DTB so my initial overlay is enough. I did have to set the pinmux to your settings:

Bank: 0 Reg: 0x0243d010 Val: 0x00000448 → spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 → spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 → spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 → spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 → spi1_mosi_pz5

Otherwise the pins are forced to a GPIO function I think.

Thanks for your help!