Jetson-xavier-nx-devkit how to enable spi0

Hi,
How to enable SPI0/1 in 40-Pin Expansion Header, and How to ensure the multiplex pin as SPI function?

Have a reference to below link for it.

https://www.jetsonhacks.com/2020/05/04/spi-on-jetson-using-jetson-io/

Hi,
SPI1 has been configured as post, and loopback test is ok, but no response when connect spi device.
loopback test:
root@insta360-desktop:/vendor/system/insta360/bin# ./spidev_test -D /dev/spidev0.0 -s 1000000 -p"\xf5\x00" -v
spi mode: 0x0
bits per word: 8
max speed: 1000000 Hz (1000 KHz)
TX | F5 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | �.
RX | F5 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | �.
I want to make sure of a few things:
1.The device file corresponding to SPI1 is spidev0.X ?
2.Pinmux configure is all right?
root@insta360-desktop:/sys/kernel/debug# cat tegra_pinctrl_reg | grep spi1
Bank: 0 Reg: 0x0243b030 Val: 0x00023415 → qspi1_io3_pd3
Bank: 0 Reg: 0x0243b038 Val: 0x00023415 → qspi1_io2_pd2
Bank: 0 Reg: 0x0243b040 Val: 0x00023415 → qspi1_io1_pd1
Bank: 0 Reg: 0x0243b048 Val: 0x00023415 → qspi1_io0_pd0
Bank: 0 Reg: 0x0243b050 Val: 0x00023435 → qspi1_sck_pc6
Bank: 0 Reg: 0x0243b058 Val: 0x00023415 → qspi1_cs_n_pc7
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 → spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 → spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 → spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 → spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 → spi1_mosi_pz5
root@insta360-desktop:/sys/kernel/debug#

No, SPI1 pin 13,16,18,22 is spidev2.x SPI0_xx pin 19,21,23,24 is the spidev0.x