The documentation contains the below text, with the description of the DT entry being empty.
I would have expected to see
When the codec operates in master mode, the codec I2S bit clock typically is driven by the codec’s internal PLL, which is driven in turn by a fixed rate external clock source. The properties below must be set in the appropriate DAI link to indicate that the codec should operate in master mode.
The R28 documentation does not cover this topic.