I am designing a system based on Jeston TX2/TX2i module. I am using a PCIe switch to connect to four mini PCIe cards. I am using PCIe0 root port on TX2 to connect to the PCIe switch. The downports (all x1) from the switch is connected to four miniPCIe cards. I am also using a clock buffer which takes the reference clocks from Jetson module as input and outputs clocks to each of the minPCIe cards based on the clkreq# signal from each of these mini PCIe cards. I am not sure about the status of PEX0_CLKREQ# pin on the TX2 module. Can i leave it NC in this scenario?