Thanks for your generic comment.
In more details, I’d like to control the GPIO2/CAM0_RST# and the GPIO3/CAM1_RST# from the TX1 flashed by JetPack310 (L4T R28.1).
On the spreadsheet “Jetson_TX1_Generic_Customer_Pinmux_Customer_Release.xlsm”,
the GPIO2/CAM0_RST# is defined as GPIO3_PS_04 and
the GPIO3/CAM1_RST# is defined as GPIO3_PS_05.
I downloaded the source of L4T R28.1 and I refered to /hardware/nvidia/platform/t210/jetson/kernel-dts/jetson-platforms/tegra210-jetson-e-gpio-p2530-0930-e03.dtsi.
This file includes following.
TEGRA_GPIO(S, 4) 0
TEGRA_GPIO(S, 5) 0
The macro TEGRA_GPIO() is defined in the /hardware/nvidia/soc/tegra/kernel-include/dt-bindings/gpio/tegra-gpio.h.
#define TEGRA_GPIO_BANK_ID_S 18
#define TEGRA_GPIO(bank, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
So, I think the GPIO number is correct…
GPIO2/CAM0_RST# is (188 + 4) = 148
GPIO3/CAM1_RST# is (188 + 5) = 149
In act, the CAM1_RST# can be controlled by GPIO149.
I hope NVIDIA give me something information.