How to change the number of PCIe lanes(from Width x1 to Width x8)

I check PCIe version and lanes in my orin host with following commands:

# 0001:00:00.0 PCI bridge: NVIDIA Corporation Device 229e (rev a1)
# 0001:01:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8822CE 802.11ac PCIe Wireless Network Adapter
lspci -n | fgrep 0001:00:00.0
# 0001:00:00.0 0604: 10de:229e (rev a1)
lspci -n -d 10de:229e -vvv | fgrep width -i
# LnkCap:	Port #0, Speed 16GT/s, Width x1, ASPM not supported
# LnkSta:	Speed 2.5GT/s (downgraded), Width x1 (ok)

From the information displayed above, it is PCIe gen 4.0, *1.

gen4.0 is as expected, but how do I set x8 lanes ?


The pcie controller on the m.2 slot of Orin devkit only has x1 lane hardware.

We use the PCIe x16 connector on the J6 slot:

I guess there is someting wrong with link training.

So how can i debug the link training. Are there any operational documents related to linke training?


What goes wrong is the info you are checking.

You said you are using a x16 slot, but the lspci info you are trying to dump is not the controller for the x16 slot…

As your own info shows, 0001:xxxxx controller has a PCIe Wireless Network Adapter on it. So obviously not your x16 slot… this is another pcie controller…

In case you don’t know, there are multiple pcie controller on jetson orin…

What is the exact thing you are trying here? Still PCIe endpoint?

Yes, after I have successfully tested Bidirectional Data Transfer

I want to try to test data transfer performance, when I execute lspci in orin, I can only see two devices 0001:00:00.0 and 0001:01:00.0

So are there any steps I’m missing here?

What is the exact device you want to test here? I cannot answer what is missing here because I totally not sure what you are trying to do.

OK,I try to describe it clearly.

Before, I tested Bidirectional Data Transfer between Orin device(EP) and x86 device (RP) successfully.

See previous discussion for details:

Now, I want to test the performance of the data transfer between Orin and x86.

From the Hardware Layout Info:


I thought the theoretical bandwidth of transmission was 16GB/s (gen4.0, *8)

But from the pci information I see on the EP side (Orin), the width is only x1.

I read the documentation of EP Mode again:

It seems to require me to rewrite the nvidia/drivers/pci/dwc/pcie-tegra.c file ?

I’m sorry that I have relatively little experience in kernel and drivers, and I’m still learning by doing. If the information I provided is still not enough, you can bring it up and I’ll continue to add.

Thx :)


Ok, so it is still the EP issue. But why are you probing the device info of the wireless wifi card of jetson?

Your should check the lspci device on your host side but not check another random controller on jetson device and ask why it is only x1? Of course that is x1 because you are totally checking another hardware.

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I probably understand that from the RP side (x86 host), the shared RAM device is indeed 16GT/s, x8:
(The actual trained speed is 8GT/s & x8, which should be related to the x86 device)

root@x86:~# lspci | fgrep RAM | fgrep NVIDIA
06:00.0 RAM memory: NVIDIA Corporation Device 0001
root@x86:~# lspci -n -s 06:00.0
06:00.0 0500: 10de:0001
root@x86:~# lspci -n -d 10de:0001 -vvv | fgrep speed -i
		LnkCap:	Port #0, Speed 16GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <1us, L1 <64us
		LnkSta:	Speed 8GT/s (downgraded), Width x8 (ok)
		LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-

Thank you brother for your patient reply !

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