How to enable spi0,spi1 and spi2 on jetson tx2 EVK

I don’t understand the question. Could you give more detail information.

i mean to say spidev0.0 and spi3.0 i am able to create but when i am adding spidev in spi1 and spi2 this sidev1.0 and 2.0 i am not getting,i want to check all 4 spi0,spi1,spi2 and spi3 lines using spidev

Did you add the spi@0/spi@1 in the spi@xxxx scope? Also check the status is “okay”
BTW looks like spi2 didn’t pin out to external pin header to use.

spi@3220000 {
status = “okay”;
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x8>;
nvidia,tx-clk-tap-delay = <0x16>;
};
};

    };

This is my entry for spi1 but spidev1.0 is not creating…

Could you confirm the context in the /proc/device-tree

Looks like there’s no spi@3220000 on TX2.

                spi0 = "/spi@3210000";
                spi1 = "/spi@c260000";
                spi2 = "/spi@3230000";
                spi3 = "/spi@3240000";

root@localhost:/home/ubuntu# sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi

Bank: 0 Reg: 0x0243b000 Val: 0x00000415 → qspi_io3_pr4
Bank: 0 Reg: 0x0243b008 Val: 0x00000001 → qspi_io2_pr3
Bank: 0 Reg: 0x0243b010 Val: 0x00000001 → qspi_io1_pr2
Bank: 0 Reg: 0x0243b018 Val: 0x00000001 → qspi_io0_pr1
Bank: 0 Reg: 0x0243b020 Val: 0x00000001 → qspi_sck_pr0
Bank: 0 Reg: 0x0243b028 Val: 0x00000049 → qspi_cs_n_pr5
Bank: 0 Reg: 0x0243b030 Val: 0x00002000 → qspi_comp

i am only getting these output,i think pinmux value is not getting reflected,right?

do i need to update the pinmux sheet for this,i have only replaced the value

for spi0 i am getting this register setting

Bank: 0 Reg: 0x0243d000 Val: 0x0000040a → gpio_wan8_ph3
Bank: 0 Reg: 0x0243d008 Val: 0x00000046 → gpio_wan7_ph2
Bank: 0 Reg: 0x0243d010 Val: 0x00000456 → gpio_wan6_ph1
Bank: 0 Reg: 0x0243d018 Val: 0x00000046 → gpio_wan5_ph0

do i need to change the ph0 and ph2 setting, i hardcoded with 406 in cfg file but it is not reflecting

Did you use TX2? Did you use the customization dtb? You may remove others spi pinmux configure from the device tree. Have a verify with the original dtb to confirm it.

yes i am using Tx2 with SDK 32.4.3, i am using customize dtb but i have not done changes for SPI,it is same as original that comes with tx2 EVK.

we can verify it in EVK also right?

if i see pinmux sheet for spi0 they have mention this pin,is this understanding correct.

SPI0_CLK E3 GPIO_SEN1 E24 E24 unused_GPIO_SEN1
SPI0_MISO E4 GPIO_SEN2 D25 E26 unused_GPIO_SEN2
SPI0_MOSI F4 GPIO_SEN3 C27 F25 unused_GPIO_SEN3
SPI0_CS0# F3 GPIO_SEN4 F24 G24 unused_GPIO_SEN4

and for this spi0 registers are

pinmux.0x0c302050 = 0x00000401; # gpio_sen1_pv1: spi2, tristate-disable, input-disable, lpdr-disable
pinmux.0x0c302058 = 0x00000455; # gpio_sen2_pv2: spi2, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0c302060 = 0x00000401; # gpio_sen3_pv3: spi2, tristate-disable, input-disable, lpdr-disable
pinmux.0x0c302068 = 0x00000409; # gpio_sen4_pv4: spi2, pull-up, tristate-disable, input-disable, lpdr-disable

is this correct understanding,this is spi0 setting?

The SPI0_xxx is map to spi1 aka spi@c260000,
spi0 aka spi@3210000 is the SPI1_xxxx pins

Looks like TX2 didn’t support to check by cat the sys fs.
You can confirm it with devmem2 to read the address as you list.

for spi1 what we see in pinmux sheet is

SPI1_CLK G13 GPIO_CAM4 AW33 AV30 unused_GPIO_CAM4 GPIO3_PN.03 VGP4 SPI4_SCK B B B VGP4 SPI4 RSVD2 RSVD3 RSVD2 gpio_cam4_pn3 vddio_uartcam ST BDPGLP_IFC_VXVDP1P1P1 100k pd GPIO_PN3 PULL_DOWN TRISTATE ENABLE 1 1 1 1 1 1 VALID GPIO3_PN.03 Input Int PD Disable SPI4_SCK
SPI1_MISO F14 GPIO_CAM5 BA35 AY32 unused_GPIO_CAM5 GPIO3_PN.04 VGP5 SPI4_DIN B B B VGP5 SPI4 RSVD2 RSVD3 RSVD2 gpio_cam5_pn4 vddio_uartcam ST BDPGLP_IFC_VXVDP1P1P1 100k pd GPIO_PN4 PULL_DOWN TRISTATE ENABLE 1 1 1 1 1 1 VALID GPIO3_PN.04 Input Int PD Disable SPI4_MISO
SPI1_MOSI F13 GPIO_CAM6 AY34 AW32 unused_GPIO_CAM6 GPIO3_PN.05 VGP6 SPI4_DOUT B B B VGP6 SPI4 RSVD2 RSVD3 RSVD2 gpio_cam6_pn5 vddio_uartcam ST BDPGLP_IFC_VXVDP1P1P1 100k pd GPIO_PN5 PULL_DOWN TRISTATE ENABLE 1 1 1 1 1 1 VALID GPIO3_PN.05 Input Int PD Disable SPI4_MOSI
SPI1_CS0# E14 GPIO_CAM7 AY35 AV32 unused_GPIO_CAM7 GPIO3_PN.06 SPI4_CS0 B B RSVD0 SPI4 RSVD2 RSVD3 RSVD0 gpio_cam7_pn6 vddio_uartcam ST BDPGLP_IFC_VXVDP1P1P1 100k pu GPIO_PN6 PULL_UP TRISTATE ENABLE 1 1 1 1 1 1 VALID GPIO3_PN.06 Input Int PU Disable SPI4_CS0

is this spi1?

what is the command to read register by devmem2

SPI1 is the pin name of the and you can see the SPI4_DIN is the HW function name and you can get the software spi number aka spi3 by sub 1, due to HW number start from 1 and software start from 0.

You can read the by sudo devmem2 0x0c302050

so just want to confirm SPI1 is the pin name it is the actual spi number in the software that is spi1 spi1: spi@c260000.

this is spi bus number 1 or spi bus number 3,if a slave is connected to SPI1 pin number then from software i will use spi1 or spi3,just confirm i am confused?

i got your point,SPI1 pin number is spi3 from software and spi from hardware.

spi3 controller address is @3240000 ,am i correct?

the register setting which we are doing for spi line,the 4 registers value should be same for all right i mean sclk,miso,mosi,cs for all spi line?

Suggest set like below

Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5