SPI config on TX2 R28.3

I’m trying to enable SPI on TX2 R28.3, here is my patches:

sources/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-b400-tx2-a00-00-base.dts

};
 	};
  
+//
+	spi@3240000 {
+		spi@0 {
+				compatible = "spidev";
+				reg = <0x0>;
+				spi-max-frequency = <0x1312D00>;
+				nvidia,enable-hw-based-cs;
+				nvidia,cs-setup-clk-count = <0x1e>;
+				nvidia,cs-hold-clk-count = <0x1e>;
+				nvidia,rx-clk-tap-delay = <0x1f>;
+				nvidia,tx-clk-tap-delay = <0x0>;		
+			};
+	};
+////
+
+//
+	spi@c260000 {
+		can2: can@0 {
+			compatible = "microchip,mcp2515";
+			reg = <1>;
+			spi-max-frequency = <10000000>;
+//			clocks = <&clk24m>;
+//			interrupt-parent = <&gpio4>;
+//			interrupts = <13 0x2>;
+//			vdd-supply = <&reg5v0>;
+//			xceiver-supply = <&reg5v0>;
+		};
+	};
+////
+
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x70000000>;

kernel config

@@ -1024,7 +1024,7 @@
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
-CONFIG_CAN=m
+CONFIG_CAN=y
 CONFIG_CAN_RAW=m
 CONFIG_CAN_BCM=m
 CONFIG_CAN_GW=m
@@ -1034,7 +1034,7 @@
 #
 CONFIG_CAN_VCAN=m
 CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
+CONFIG_CAN_DEV=y
 CONFIG_CAN_CALC_BITTIMING=y
 # CONFIG_CAN_LEDS is not set
 CONFIG_CAN_GRCAN=m
@@ -1069,7 +1069,7 @@
 CONFIG_CAN_PEAK_USB=m
 CONFIG_CAN_8DEV_USB=m
 CONFIG_CAN_SOFTING=m
-CONFIG_MTTCAN=m
+CONFIG_MTTCAN=y
 # CONFIG_MTTCAN_IVC is not set
 # CONFIG_CAN_DEBUG_DEVICES is not set
 CONFIG_IRDA=m
@@ -2481,7 +2481,7 @@
 #
 # SPI Protocol Masters
 #
-CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_SPIDEV=y
 CONFIG_SPI_TLE62X0=m
 CONFIG_QSPI_TEGRA186=y
 CONFIG_SPI_TEGRA186_AON=y

And then, I run below command

echo 123 > /dev/spidev3.0

it works on R28.2.1, but failed on R28.3 (by logic analyzer).

If I replace
[R28.3] Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg
with
[R28.2.1] Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg

Then R28.3 will work.

I would like to know which configs need to be modified in the tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg file (just for SPI only), instead of replacing the whole file.

Thanks.

SPI3 should be below pin

pinmux.0x02430028 = 0x00000401; # gpio_cam2_pn1: extperiph3, tristate-disable, input-disable
pinmux.0x02430038 = 0x00000401; # gpio_cam4_pn3: spi4, tristate-disable, input-disable
pinmux.0x02430040 = 0x00000455; # gpio_cam5_pn4: spi4, pull-down, tristate-enable, input-enable
pinmux.0x02430048 = 0x00000401; # gpio_cam6_pn5: spi4, tristate-disable, input-disable
pinmux.0x02430050 = 0x00000409; # gpio_cam7_pn6: spi4, pull-up, tristate-disable, input-disable

Thanks, it works now.

Hi ShaneCCC,
Do you have SPI1 pinmux values which have address (pinmux.243d018, pinmux.243d010, pinmux.243d008, pinmux.243d000 etc)?
Thanks, Jack

You can check the cfg file.
Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg

Setup in this file Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg has all SPI1 pins disabled (setup as inputs), I think.

In this file Linux_for_Tegra/bootloader/t186ref/BCT/tegra186-mb1-bct-pmic-quill-p3489-1000-a00.cfg found SPI1 pins enabled as described in https://elinux.org/Jetson/TX2_SPI for SPI4.

Question is how do we enable bootloader to take the correct config file? Or knowing which config file it uses?

Hi ShaneCCC,
I added to the following ‘dtsi’ file to enable spi0 but dmesg complaints about DMA. Here’s dmesg ouput:

ubuntu@tegra-ubuntu:~$ dmesg | grep spi
[    0.230513] iommu: Adding device 3210000.spi to group 11
[    0.230879] iommu: Adding device c260000.spi to group 12
[    0.231180] iommu: Adding device 3240000.spi to group 13
[    2.551356] spi-tegra114 3210000.spi: Static pin configuration used
[    2.551433] /spi@3210000: could not get #dma-cells for /fixed-regulators/regulator@0
[    2.551441] spi-tegra114 3210000.spi: Dma channel is not available: -19
[    2.551919] spi-tegra114 c260000.spi: Static pin configuration used
[    2.552350] spi-tegra114 3240000.spi: Static pin configuration used
[    4.196421] spi-tegra114 c260000.spi: Static pin configuration used
[    4.197277] spi-tegra114 3240000.spi: Static pin configuration used
ubuntu@tegra-ubuntu:~$ ^C

What other things need to be done for /dev/spidev0.0 to appear?

--- a/sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common-p3489-1000-a00.dtsi
+++ b/sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common-p3489-1000-a00.dtsi
@@ -42,7 +42,33 @@
        };
 
        spi@3210000 {
+               reg = <0x0 0x3210000 0x0 0x10000>;
+               dmas = <0x19 0xf 0x19 0xf>;
+               interrupts = <0x0 0x24 0x4>;
+               compatible = "nvidia,tegra186-spi";
+               clock-names = "spi", "pll_p", "clk_m";
+               reset-names = "spi";
+               clocks = <0xd 0x31 0xd 0x10d 0xd 0x261>;
+               nvidia,dma-request-selector = <0x19 0xf>;
+               resets = <0xd 0x28>;
                status = "okay";
+               #address-cells = <0x1>;
+               phandle = <0x7d>;
+               nvidia,clk-parents = "pll_p", "clk_m";
+               #stream-id-cells = <0x1>;
+               #size-cells = <0x0>;
+               dma-names = "rx", "tx";
+               linux,phandle = <0x7d>;
+               spi@0 {
+                       compatible = "spidev";
+                       reg = <0x0>;
+                       spi-max-frequency = <0x1312D00>;
+                       nvidia,enable-hw-based-cs;
+                       nvidia,cs-setup-clk-count = <0x1e>;
+                       nvidia,cs-hold-clk-count = <0x1e>;
+                       nvidia,rx-clk-tap-delay = <0x1f>;
+                       nvidia,tx-clk-tap-delau = <0x0>;
+               }; 
        };
 
        spi@3240000 {
j

Hi ShaneCCC,

By commenting out ‘dma’ and ‘interrupts’ definitions in the above dtsi file, I now can see /dev/spidev.0.0.
Used spidev_test for output to SPI0 and by probing device interface pins, I don’t see any activities.
Then I used ‘devmem2’ to read out pinmux values which matched with what’s in tegra186-mb1-bct-pinmux-quill-p3489-1000-a00.cfg.

pinmux.0x0243d018 = 0x00000402; # gpio_wan5_ph0: spi1, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d010 = 0x00000456; # gpio_wan6_ph1: spi1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d008 = 0x00000402; # gpio_wan7_ph2: spi1, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d000 = 0x0000040a; # gpio_wan8_ph3: spi1, pull-up, tristate-disable, input-disable, lpdr-disable

What else should I check next for gaining SPI bus activities?

Thanks,
Jack

Hi ShaneCCC,

Can I modify pinmux setting by using devmem2 and retest by spidev_test? Or have to modify .cfg file in the bootloader to take effect.

Thanks,
Jack

Both of them are fine.

Hi ShaneCCC,

Put some dev_dbg statements inside ‘tegra_spi_start_cpu_based_transfer’ and see the fifo cleared after bytes written to fifo. But still there’s no SPI0 pin signal activities.

On the ‘dtsi’ file change:
Does it matter if the ‘dmas’ and ‘interrupts’ are commented out?

spi@3210000 {
+               reg = <0x0 0x3210000 0x0 0x10000>;
+//               dmas = <0x19 0xf 0x19 0xf>;
+//               interrupts = <0x0 0x24 0x4>;
+               compatible = "nvidia,tegra186-spi";

What would you suggest I check next?

Thanks,
Jack

Hi ShaneCCC,

Can pinmux be configured on the fly using devmem2?
I’ve changed all SPI2 pins to be pulled up (values 0x014) on the Jetson TX2 board and all pins J19, J21, J23 stayed low.

Can you reply please?

Thanks,
Jack

Tried both values 0x014 as pulled down and 0x018 or 0x008 as pulled up, all SPI1 pins stayed down.
The registers are 0xC3022050, 0xC3022058, 0xC3022060, 0xC3022068.

@jack
Yes the pinmux can be configured on fly using memory tools.
The J19, J21, J23 did you mean pin 19, 21, 23, 24 of the J21?
Could you confirm the SPI0 working well for you first?

@ShaneCCC SPI0 does not work, no signal on the pins.

On the eval board, found the confusion point:
1, Schematics shows SPI1 connected to J21 debug headers.
2, PinMux spreadsheet shows SPI1 of schematics is using SPI4 pinmux.
3, SW should setup SPI4 as /dev/spidev3.0 to send output to J21 headers (labeled as SPI1!).

So my next task is to decide HW SPI0 thru pinmux mapping to use SW /dev/spidev2.0 on the custom board.

Why is there a such disconnect between SPI labeling? Is this also true throughout?