how to enable the vsync in opengl application?

when display the image by direct fb, there is screen tearing, could i eliminate it by open the vsync, open it will call the code below code in kernel ?
int tegra_dc_wait_for_vsync(struct tegra_dc dc)
{
unsigned long timeout_ms;
unsigned long refresh; /
in 1000th Hz */
int ret;

mutex_lock(&dc->lp_lock);
mutex_lock(&dc->lock);
if (!dc->enabled) {
	ret = -ENOTTY;
	goto out;
}
refresh = tegra_dc_calc_refresh(&dc->mode);
/* time out if waiting took more than 2 frames */
timeout_ms = DIV_ROUND_UP(2 * 1000000, refresh);
_tegra_dc_user_vsync_enable(dc, true);
mutex_unlock(&dc->lock);
ret = wait_for_completion_interruptible_timeout(
	&dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
mutex_lock(&dc->lock);
_tegra_dc_user_vsync_enable(dc, false);

out:
mutex_unlock(&dc->lock);
mutex_unlock(&dc->lp_lock);
return ret;
}

Hi Chenghaibo,

Have you tried https://devtalk.nvidia.com/default/topic/932150/enabling-disabling-vsync-jetson-tx1-/ ?

Hi Chenghaibo,

I use a simple gl application with vsync enable and the kernel code above is not called.

You can enable/disable vsync by export __GL_SYNC_TO_VBLANK=1/0.

You can take a look at /kernel/drivers/video/tegra/dc/window.c: _tegra_dc_program_windows(…)

This function is the one called when vsync enable by GL API.

thank you very much, It looks like, the vsync might be enabled by default, under the X11 environment, the tegra_dc_ext_flip was called by 60HZ, and the image looks like perfect with out any screen tearing, but under the direct fb, for purpose of eliminate the tear, i call the tegra_dc_wait_for_vsync,but that is useless, should i use the tegra_fb_blank??

Only fb.c and dev.c can receive the ioctl calls from user space.

I am still looking into it, but you can try tegra_fb_blank first.

Hi Chenghaibo,

How is your app going?

I’m sorry for communicate with you so late, in company, if i submit my reply, my account will be logout.

during present, i can’t find out which code relate to the screen tear.

below is my guess

the cea-861-d notice the 1920x1080 at 59.94 Hz
total H line:2200;
total v line:1125;
vblank is 45 line;

so, if the dma can’t transfer 1920x1080x4 byte per (45 /(59.94 x 1125) ) seconds that equal to
12429MB / S, it is a huge number, so the data should be transferred during the active period.

i hope my guess could help you

Hi Chenghaibo,

Could you print the return value of ioctl FBIO_WAITFORVSYNC ?

I have tried to flip framebuffer with FBIOPAN_DISPLAY. If WAITFORVSYNC is called, I can see smooth result.

However, I didn’t test it with any cuda kernel. Only used cpu to keep drawing framebuffer.