How to use SPI-CAN module on Jetson Nano 2GB

Hi, everyone.
I want to know how to use SPI-CAN module connected to Jetson Nano 2GB. There are some topics about SPI-CAN for Jetson Nano (4GB), like
Jetson nano and mcp2515 can module - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums
Jetson Nano and MCP2515 Can Module

but I can’t find topics or reference for 2GB model.
I updated Jetpack to 4.5 and I find there are two dtbos for mcp251x below.

tegra210-p3448-0000-p3449-0000-a01-mcp251x.dtbo
tegra210-p3448-0000-p3449-0000-a02-mcp251x.dtbo

But what I want to use is a dtbo for 2GB model, like this.
tegra210-p3448-0003-p3542-0000-mcp251x.dtbo

When I run jetson-io and enter the page, “Configure Jetson for compatible hardware”, I can’t find an item for mcp251x.

What should I do ?
Any answers would be appreciated.

Thanks.

Sorry for the late response, may I know this is still an issue to resolve?

Thanks

Hi,
MCP SW is not fully supported in Nano 2GB currently.
For you , I have attached dtb to try out.
tegra210-p3448-0003-p3542-0000-mcp251x.dtbo (3.2 KB)
Copy this in /boot/ folder of the device. and run jetson-io

Thank you for your replay, kayccc.
I made a little step but I still can’t use can modules.
I describe my situation and what I’ve done.

I bought two SPI-CAN modules with 8 MHz clock, 5V torrelant.

I made changes to the modules.
1.
Modify circuit (cut line and append pin for 5V) to use 3.3V according to this web ( [quick-guide] CAN bus on raspberry pi with MCP2515 - Raspberry Pi Forums)
2.
Put a jumper head on J1 pins to enable a terminal register (120 ohm).

Then I connected these modules to Jetson Nano 2GB.

for can0
No. can Jetson
1 INT INT(31)
2 SCK SCK(23)
3 SI MOSI(19)
4 SO MISO(21)
5 CS CS0(24)
6 GND GND
7 VCC 3.3V
8 5V 5V

for can1
No. can Jetson
1 INT INT(32)
2 SCK SCK(13)
3 SI MOSI(37)
4 SO MISO(22)
5 CS CS0(18)
6 GND GND
7 VCC 3.3V
8 5V 5V

5V above is the pin I added.

And I connected two modules.
can0 can1
CAN H CAN H
CAN L CAN L

Then I started to make dtbo.
I downloaded source code and copied tegra210-p3448-0000-p3449-0000-a01-mcp251x.dts to tegra210-p3448-0003-p3542-0000-mcp251x.dts and changed clock.

I’m not sure if the value for 8MHz should be 8000000 or 16000000.
Here is dts file for 16000000 (tegra210-p3448-0003-p3542-0000-mcp251x.dts).

// SPDX-License-Identifier: GPL-2.0-only
/*

  • Jetson Device-tree overlay for MCP251x CAN Controller.
  • Copyright © 2020 NVIDIA CORPORATION. All rights reserved.

*/

#include <dt-bindings/pinctrl/pinctrl-tegra.h>

/ {
overlay-name = “MCP251x CAN Controller”;
compatible = JETSON_COMPATIBLE;

    fragment@0 {
            target-path = "/";
            __overlay__ {
                    clocks {
                            can_clock: can_clock {
                                    compatible =  "fixed-clock";
                                    #clock-cells = <0>;
                                    clock-frequency =  <16000000>;
                                    clock-accuracy = <100>;
                            };
                    };
            };
    };

    fragment@1 {
            target = <&hdr40_spi1>;
            __overlay__ {
                    spi@0 {
                            compatible =  "microchip,mcp2515";
                            reg = <0x0>;
                            spi-max-frequency = <10000000>;
                            nvidia,enable-hw-based-cs;
                            nvidia,rx-clk-tap-delay = <0x7>;
                            clocks = <&can_clock>;
                            interrupt-parent = <&gpio>;
                            interrupts = <HDR40_PIN31_GPIO  0x1>;
                            controller-data {
                                     nvidia,cs-setup-clk-count = <0x1e>;
                                    nvidia,cs-hold-clk-count  = <0x1e>;
                                    nvidia,rx-clk-tap-delay  = <0x1f>;
                                    nvidia,tx-clk-tap-delay  = <0x0>;
                            };
                    };
            };
    };

    fragment@2 {
            target = <&pinmux>;
            __overlay__ {
                    pinctrl-names = "default";
                    pinctrl-0 = <&hdr40_pinmux>;

                    hdr40_pinmux: header-40pin-pinmux {
                            pin19 {
                                    nvidia,pins =  HDR40_PIN19;
                                    nvidia,function =  HDR40_SPI;
                                    nvidia,pull =  <TEGRA_PIN_PULL_DOWN>;
                                    nvidia,tristate =  <TEGRA_PIN_DISABLE>;
                                    nvidia,enable-input =  <TEGRA_PIN_DISABLE>;
                            };
                            pin21 {
                                    nvidia,pins =  HDR40_PIN21;
                                    nvidia,function =  HDR40_SPI;
                                    nvidia,pull =  <TEGRA_PIN_PULL_DOWN>;
                                    nvidia,tristate =  <TEGRA_PIN_DISABLE>;
                                    nvidia,enable-input =  <TEGRA_PIN_ENABLE>;
                            };
                            pin23 {
                                    nvidia,pins =  HDR40_PIN23;
                                    nvidia,function =  HDR40_SPI;
                                    nvidia,pull =  <TEGRA_PIN_PULL_DOWN>;
                                    nvidia,tristate =  <TEGRA_PIN_DISABLE>;
                                    nvidia,enable-input =  <TEGRA_PIN_ENABLE>;
                            };
                            pin24 {
                                    nvidia,pins =  HDR40_PIN24;
                                    nvidia,function =  HDR40_SPI;
                                    nvidia,pull =  <TEGRA_PIN_PULL_UP>;
                                    nvidia,tristate =  <TEGRA_PIN_DISABLE>;
                                    nvidia,enable-input =  <TEGRA_PIN_DISABLE>;
                            };
                            pin26 {
                                    nvidia,pins =  HDR40_PIN26;
                                    nvidia,function =  HDR40_SPI;
                                    nvidia,pull =  <TEGRA_PIN_PULL_UP>;
                                    nvidia,tristate =  <TEGRA_PIN_DISABLE>;
                                    nvidia,enable-input =  <TEGRA_PIN_DISABLE>;
                            };
                    };
            };
    };

};

Then I built dtbo using ‘make -j4 dtbs’ and copied the dtbo to /boot.
I ran jetson-io and selected ‘MCP251x CAN Controller’ and rebooted Jetson.

Then I did below.

ls /dev/spi*
/dev/spidev0.1 /dev/spidev1.1

dmesg | grep spi
[ 0.450856] iommu: Adding device 7000d400.spi to group 7
[ 0.451125] iommu: Adding device 7000d600.spi to group 8
[ 0.451435] iommu: Adding device 70410000.spi to group 9
[ 3.427430] tegra-qspi 70410000.spi: Prod settings list not found
[ 3.434620] qspi_mtd spi32766.0: MX25U3235F (4096 Kbytes)
[ 3.440077] qspi_mtd spi32766.0: mtd .name = spi32766.0, .size = 0x400000 (4MiB) .erasesize = 0x0000
1000 (4KiB) .numeraseregions = 0
[ 47.710410] mcp251x spi0.0 can0: MCP2515 successfully initialized.
[ 47.721315] mcp251x spi1.0 can1: MCP2515 successfully initialized.

dmesg | grep can
[ 0.000000] OF: fdt:memory scan node memory@80000000, reg size 48,
[ 1.054446] tegra-pwm 7000a000.pwm: PWM clk cannot sleep in ops
[ 47.710410] mcp251x spi0.0 can0: MCP2515 successfully initialized.
[ 47.721315] mcp251x spi1.0 can1: MCP2515 successfully initialized.

sudo ip link set can0 up type can bitrate 500000
sudo ip link set can1 up type can bitrate 500000

cat /proc/interrupts | grep mcp
265: 0 0 0 0 GPIO 168 Edge mcp251x
297: 0 0 0 0 GPIO 200 Edge mcp251x

dmesg | grep can
[ 0.000000] OF: fdt:memory scan node memory@80000000, reg size 48,
[ 1.062019] tegra-pwm 7000a000.pwm: PWM clk cannot sleep in ops
[ 51.573207] mcp251x spi0.0 can0: MCP2515 successfully initialized.
[ 51.584179] mcp251x spi1.0 can1: MCP2515 successfully initialized.
[ 231.610498] IPv6: ADDRCONF(NETDEV_UP): can0: link is not ready
[ 231.610611] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
[ 239.823915] IPv6: ADDRCONF(NETDEV_UP): can1: link is not ready
[ 239.824491] IPv6: ADDRCONF(NETDEV_CHANGE): can1: link becomes ready

sudo cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 0-255, parent: platform/6000d000.gpio, tegra-gpio:

gpio-12 (SPI1_MOSI )
gpio-13 (SPI1_MISO )
gpio-14 (SPI1_SCK )
gpio-15 (SPI1_CS0 )
gpio-16 (SPI0_MOSI )
gpio-17 (SPI0_MISO )
gpio-18 (SPI0_SCK )
gpio-19 (SPI0_CS0 )
gpio-20 (SPI0_CS1 )

gpio-168 (GPIO07 )

gpio-200 (GPIO11 )

I tried to communicate with cans.
I ran below command on a terminal.
candump -x any

And then I ran below on another terminal.
cansend can0 123#abcdabcd

Unfortunately, nothing is happened.

I watched INT pins of two can modules when I did cansend using oscilloscope, but signals remained as 3.3V.

Seems no packets are transferred.

ip -s -d link show can0
4: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UP mode DEFAULT group default qlen 10
link/can promiscuity 0
can state ERROR-ACTIVE restart-ms 0
bitrate 500000 sample-point 0.875
tq 125 prop-seg 6 phase-seg1 7 phase-seg2 2 sjw 1
mcp251x: tseg1 3…16 tseg2 2…8 sjw 1…4 brp 1…64 brp-inc 1
clock 8000000
re-started bus-errors arbit-lost error-warn error-pass bus-off
0 0 0 0 0 0 numtxqueues 1 numrxqueues 1
gso_max_size 65536 gso_max_segs 65535
RX: bytes packets errors dropped overrun mcast
0 0 0 0 0 0
TX: bytes packets errors dropped carrier collsns
0 0 0 0 0 0

ip -s -d link show can1
5: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UP mode DEFAULT group default qlen 10
link/can promiscuity 0
can state ERROR-ACTIVE restart-ms 0
bitrate 500000 sample-point 0.875
tq 125 prop-seg 6 phase-seg1 7 phase-seg2 2 sjw 1
mcp251x: tseg1 3…16 tseg2 2…8 sjw 1…4 brp 1…64 brp-inc 1
clock 8000000
re-started bus-errors arbit-lost error-warn error-pass bus-off
0 0 0 0 0 0 numtxqueues 1 numrxqueues 1
gso_max_size 65536 gso_max_segs 65535
RX: bytes packets errors dropped overrun mcast
0 0 0 0 0 0
TX: bytes packets errors dropped carrier collsns
0 0 0 0 0 0

Any help would be appreciated.

Thank you for your advice, shgarg.
Although the clock is not for 8MHz module, I tried and I couldn’t.

Hi,
In this dts file, can you try making below changes and check?
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
everywhere, keep it input enable where ever it is disable.

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