I2C base address mapping vs pin name

We are hard at work mapping TX2 hardware pins (recognizeable on our schematic) to base addresses (hopefully recognizeable by the device tree).

So far we have found one mapping table in this forum:

  1. i2c0 = “/i2c@3160000”;
  2. i2c1 = “/i2c@c240000”;
  3. i2c2 = “/i2c@3180000”;
  4. i2c3 = “/i2c@3190000”;
  5. i2c4 = “/bpmp_i2c”;
  6. i2c5 = “/i2c@31b0000”;
  7. i2c6 = “/i2c@31c0000”;
  8. i2c7 = “/i2c@c250000”;
  9. i2c8 = “/i2c@31e0000”;

This brings up two new questions:

  1. Most of this looks like numerical base addresses, just not bpmp_i2c. What is the format definition of these mappings and where are they defined?

  2. Actual hardware pins on the TX2 have names like “I2C_GP1”, “I2C_CAM” etc. Where is the mapping between those and the entries in the table above?


I am also wondering about this!

You can check it in the Jetson TX2 Pinmux, available in the Jetson Download Center. It is mapped this way:

  • I2C1_DAT/CLK => I2C_GP1_DAT/CLK => i2c@3160000
  • I2C2_DAT/CLK => I2C_GP0_DAT/CLK => i2c@c240000
  • I2C3_DAT/CLK => I2C_CAM_DAT/CLK => i2c@3180000
  • I2C7_DAT/CLK => I2C_GP2_DAT/CLK => i2c@31c0000
  • I2C8_DAT/CLK => I2C_GP3_DAT/CLK => i2c@c250000
  • I2C9_DAT/CLK => I2C_PM_DAT/CLK => i2c@31e0000
  • You can find more details here

    Thank you for providing this table mapping the I2C aliases!

    But when I open the document I don’t see the base addresses there.

    I’m still confused here, for two reasons:

    • Is there an official table which shows what you just pasted in?

    • After parsing device tree files for the better part of a day, it looks like you count the I2C buses from 1 while other litterature counts from 0.

    @Nvidia: The current state of documentation keeps electrical engineers reasonably happy with names like “I2C_GP0” and core programmers reasonably happy with “i2c@3160000”. But when we work together it is hard to see overlaps in our documentation.


    Hi borgeqm27i,
    You can find that mapping in the Table 2: System Address Map (Page 49) of the NVIDIA Parker Series SoC TECHNICAL REFERENCE MANUAL (If it doesn’t work the link, type “Tegra X2 (Parker Series SoC) Technical Reference Manual” in the Jetson Download Center, you need to accept some EULA conditions)

    Then you have the Jetson_TX2_Series_Pin_and_Function_Names_guide_Application_Note that shows the name associations.

    Thank you!