Hello all,
I’m currently investigating the boot process of the TX1 in order to implement a low-level feature for a client. My question is about the following console prints:
[0004.763] LPDDR4 Training: Number of tables = 10
[0004.767] EMC Training (SRC-freq: 204000; DST-freq: 408000)
[0004.774] EMC Training Successful
[0004.777] EMC Training (SRC-freq: 204000; DST-freq: 665600)
[0004.783] EMC Training Successful
[0004.786] EMC Training (SRC-freq: 204000; DST-freq: 800000)
[0004.797] EMC Training Successful
[0004.800] EMC Training (SRC-freq: 204000; DST-freq: 1065600)
[0004.823] EMC Training Successful
[0004.826] EMC Training (SRC-freq: 204000; DST-freq: 1331200)
[0004.849] EMC Training Successful
[0004.852] EMC Training (SRC-freq: 204000; DST-freq: 1600000)
[0004.872] EMC Training Successful
[0004.875] Switching to 800000 KHz Success
[0004.918] LPDDR4 Training: Number of tables = 10
From my understanding these traces are not from u-boot.bin (which is executed just after) but from the nvtboot_cpu.bin binary. I found nothing in the NVIDIA documentation except that this is a “CPU part of Tegraboot for TLK hand over transition.”
I assumed it is related to the External Memory Controller (EMC) configuration, but could it be possible to have more details about the execution performed here?